Apr 2018 – Oct 2019 · 1 yr 6 mos · Karnataka, India

• Working as Program Manager
• Managing Key Accounts
• Design and Verification of SoC/ASIC/FPGA
• Leading and supervising team of around ~25-30 Engineers and guiding them in their career development
• Interacting with the client and achieving all the milestones with maximum customer satisfaction
• Responsible for Training, development & mentoring team members

Dec 2010 – Mar 2018 · 7 yrs 3 mos

• Key Responsibilities
• Involved in development life cycle phases of requirement, design, development and integration with keen customer centric focus
• Responsible for schedule preparation, schedule monitoring and successful delivery of the project to the client
• Manage project portfolio and develop project roadmap
• Design/ Verification of SOC/ASIC/FPGA and hands-on knowledge in CDV (Constraint Driven Verification), UVM/OVM/SV
• Implement and promote best standard processes and practices
• Proficient in driving overall growth and account management of an existing customer base by increasing account penetration
• Interacting with Managers of other support verticals for smooth functioning
• Interacting with client and achieving milestones on time with maximum customer satisfaction
• Develop training and assessment modules for newcomers
• Leading, supervising and guiding team in their career development
• Evaluate the performance of team members and determine their training needs and develop their IDP
• Key Achievements
• Received “Spot Award” for my contribution in Aerspace (PnB Design) project in HCL
• Received “Star Performer” award for my contribution to various projects in HCL
• Appreciated by client(INTEL) for successful tapeout of SOC for FPGA prototyping and support during Post Silicon Validation
• Received best project award in various quarters by absorbing client’s delay in giving Specification/CRs and delivering projects before schedule. This has helped in achieving CSAT scores of 7/7.

Sep 2007 – Dec 2010 · 3 yrs 3 mos · Gurgaon, India

• Key Responsibilities
• Gathering requirements and creation of high level as well as detailed level design documents
• Design and development of various FPGA and CPLD
• System Design using off the shelf ASIC and integrating them in current products portfolio
• Managing the project execution from its inception till verification and validation phase
• Convert/Port ASIC/FPGA in current products as they become obsolete to reduce cost
• Worked with quality team to define/upgrade the different processes related to ASIC/FPGA development life cycle (Front End)
• Handled team of 5-6 Engineers and ensured projects are delivered on time, within budgets and meeting the prescribed quality standards
• Key Achievements
• Received excellence award for completing a project well within a given time frame with fewer resources. The schedule was pulled in by 2 weeks which was appreciated and recognized by the partner
• Appreciated for taking initiative and contributing towards the successful completion of 6325/35 FP1.3 project. Was awarded cash prize as a token of appreciation
• Received “Best Project” award for 6325/35 FP1.3 project

Jul 2005 – Aug 2007 · 2 yrs 1 mo

• Key Responsibilities
• Design and verification of CPLD/FPGA
• Also, worked on CPLD design for Interfacing with other modules

Jun 2001 – Apr 2003 · 1 yr 10 mos

• Worked on Equipment command and control application (EMCCA) system
• Worked on development and Testing of Radar GUI using C++