Bhavinkumar Padalia

Engineering Manager

Bengaluru, Karnataka, India18 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

16+ years in post silicon validation
Led diverse team of 20 engineers
Executed 6 new SOCs and 11 spin products

Stackforce AI infers this person is a Semiconductor Testing Expert with a focus on System Validation and Power Management.

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Skills

Core Skills

System ValidationPower Management Ic (pmic)Audio Amplifier TestingTest EngineeringCmos Image Sensor Testing

Other Skills

PMIC validationtest plan developmentboard developmentcharacterizationbug fillingroot cause analysisdynamic Line-Load regulationstress testingbench characterizationDSPanalog/digital mic inputhigh-performance Line outputsATE testsautotrimOTP retention flow

About

• Highly dedicated engineering manager with 16+ years of experience in post silicon validation • Experienced in hiring, mentoring and managing diverse team of 20 engineers • Expertise in leading various SOCs - Power, memory, PMIC, audio amp and image sensor • Drove validation flow and methodology for power rail stress validation through collaboration with architect, design, pre-si modelling, manufacturing test, package, application, quality and reliability • Understood project goal and business requirements from business and tech leaders, and define, align and drive quality coverage with realistic schedule and resource • Speare-handed optimization of people resource and executed 6 new SOCs and 11 spin products • Taken holistic end to end ownership and drove out of scope changes in package. Which was proliferated to next product and saved package change cost and program schedule • Created next level leads by giving clarity on objective and empowering them in taking decision • Defined and developed dashboard for publishing regression reports for precise management view • Created technical culture and environment which encourages technical sharing and quick issue resolution. Team submitted and published various papers and posters • Hands on in reviewing board schematic-layout, handling lab setup and instruments, systematically debug by stepping through hardware or test code, enabling test hooks and data analysis

Experience

18 yrs 4 mos

Total Experience

6 yrs 1 mo

Average Tenure

7 yrs 2 mos

Current Experience

Intel corporation

Engineering Manager - System Validation Engineer

Feb 2019 – Present · 7 yrs 2 mos · Bangaon Area, India

Owned end to end PMIC validation includes test plan, board development, trim, characterization, PHTOL, bug filling and root cause
Guaranteed dynamic Line-Load regulation, Efficiency, Ripple, Startup time, Iq current, Sleep mode exit, UV, OV, Current and Temp protection thresholds, ADC Isense accuracy, I2C
Led validation of all power rails of SOC for ICCmax, ITDC, Vmin, Vmax and di/dt by running stress content concurrently to stress all IP together
Reduced scalability time of complex server platform from 3 weeks to 3-4 days. Improved setup stability and repeatability
Run algorithmic trainings on SOC + DDR to get best voltage and timing margins for memory data and command read and write transitions across memory matrix
Developed bios equivalent automation code for memory training and root caused issues in bios code

PMIC validationtest plan developmentboard developmentcharacterizationbug fillingroot cause analysis+4

Texas instruments

Test Engineer

Nov 2010 – Feb 2019 · 8 yrs 3 mos · Bangalore

Owned bench characterization of speaker audio amplifier and stereo audio codec with DSP includes analog/digital mic input, stereo classD, headphone, receiver, high-performance Line outputs amplifiers, ASI, I2C, SPI, PLL, Reference
Guaranteed high performance spec like THDN, efficiency, IV sense accuracy, SAR brownout threshold
Debugged critical issues of OTP, IDDQ, DAC current mismatch, Reference coupling
Implemented autotrim and OTP (one time programming) retention flow first time for new technology
Exposure to ATE tests for TTR, ATE to Bench and site to site Correlation
Developed dynamic multiplexing between device pins and multiple instruments using on board FPGA. It saved purchasing multiple costly equipment and saved manual change time and error
Implemented automated register default value checker, which saved manual effort for checking each register manually. Created pivot chart excel macro and saved repeated manual plot creation time

bench characterizationDSPanalog/digital mic inputhigh-performance Line outputsATE testsautotrim+3

Tessolve semiconductor pvt. ltd. (worked for cypress belgium)

Sr.Test Engineer

Dec 2007 – Nov 2010 · 2 yrs 11 mos

Developed ATE board and test program for CMOS image sensor
Identify issue and root caused to on board cap, helped in stabilizing wafer probing solution on Image Sensor Tester (IST)
Improved production test quality by adding BER and EVM test on FLEX ATE for RF transceiver.
Solved challenge of synchronization and remove ATE tester and board error to measure actual device performance

ATE board developmenttest program developmentwafer probingproduction test quality improvementTest EngineeringCMOS Image Sensor Testing