Chetan Goyal

Software Engineer

Rajasthan, India3 yrs 4 mos experience

Most Likely To Switch

Key Highlights

Expert in RTL design and system verification.
Developed emulation infrastructure for SERDES SoCs.
Awarded for optimizing electric vehicle battery charging.

Stackforce AI infers this person is a VLSI engineer with expertise in RTL design and system validation.

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Skills

Core Skills

Rtl DesignSystem VerificationFpga Implementation

Other Skills

Assertion Based VerificationAssertionsBattery TestingCC (Programming Language)C-asm flowCadence Schematic CaptureCadence Virtuoso Layout EditorCommunicationComputer System ValidationData IntegrityDigital ElectronicsElectrical EngineeringElectrical TechnologyEmbedded Engineers

About

Digital design engineer having an experience in RTL design and system level verification & validation. I strive to achieve quality and reliability in my work and enhance my skill set with time. Interested to work on challenging problems in the field of VLSI.

Experience

3 yrs 4 mos

Total Experience

3 yrs 1 mo

Average Tenure

2 yrs 10 mos

Current Experience

Texas instruments india

2 roles

Digital Design Engineer

Promoted

Jul 2023 – Present · 2 yrs 10 mos · Bengaluru, Karnataka, India · On-site

Working with FPD Link group
1. Developed palladium and FPGA emulation flow for pre-sillicon validation.
2. Undertook system level verification of cpu subsystem involving testplan creation, test structure creation, test implementation and signoff for tapeout.
3. Built Micro architecture and designed Link layer for FPD4 protocol.

PalladiumFPGASystemVerilogUVMPythonC+2

Digital Design Engineer

Jan 2023 – Jun 2023 · 5 mos · Bengaluru, Karnataka, India · On-site

1. Phy-level clock recovery circuit
2. Link Layer transmitter for serdes
3. FPGA implementation of serdes link
skills: RTL, FPGA, vivado

RTLFPGAVivadoRTL DesignFPGA Implementation

Texas instruments

2 roles

Digital Design Engineer

Promoted

Jul 2023 – Present · 2 yrs 10 mos

Emulation and FPGA based Pre-Si Validation
Designed and Deployed Cadence Palladium-based emulation infrastructure enabling first-pass validation of roughly 30M gate SERDES SoCs.
Created and maintained chip-level emulation enviroments, developing reusable models and wrappers that supported functional, performance and software validataion testbenches.
Led a team of 3 engineers in executing emulation-based pre-sillicon validation, coordinating debug efforts and accelerating system bring-up.
Developed bring-up and feature usage guides during emulation, enabling post-silicon teams and customers to accelerate DUT validation.
Automated Synthesis flow for FPGA on vivado and Validated SerDes link using the flow with reduced manpower time.
Tech Stack: Palladium, Vivado, FPGA, TCL, Python, Confluence
Link Layer Design
Designed microarchitecture for link- layer block and implemented it along with assertion-based verification.
Integrated CRC, ECC , descrambing and 8b-10b encoding mechanisms to ensure data integrity and robust communication.
Enabled data support for data rates of 7.5 Gbps along with reverse-direction control channel with 50Mbps data rate.
Tech Stack: Assertions, Cadence Simulator, SystemVerilog
CPU Subsystem Verification
Verified CPU subsystem (Cortex-R5 based) using UVM agents based testbench.
Developed constrained-random and directed tests to validate memory, register accesses, interrupts, abritration and performance - automated regressions for signoff.
Tech Stack: SystemVerilog, UVM, Python, C, Vmanager, Arm R5, Processors

PalladiumVivadoFPGATCLPythonRTL Design+1

Digital Specialist

Jan 2023 – Jul 2023 · 6 mos

• Implemented Serdes Link on FPGA including transmitter, receiver and oversampling-based Clock recovery blocks at 50 Mbps data rate.

Bharat petroleum corporation limited

Electrical Engineering Intern

Jun 2022 – Jul 2022 · 1 mo · Greater noida · On-site

Awarded Excellence Certificate for Best Internship Project.
Worked on optimizing charging time of Electric Vehicle Battery.
Modelled relationship of charging time with different battery parameters and also demonstrated their results quantitively.
Analyzed the feasibility of Redox Flow Batteries as Energy Storage Solutions. Performed a comparative analysis of them as a replacement of diesel-generators used for energy requirements of premises.