Aarushi Jain — Software Engineer
Currently working as Silicon Design Engineer. Having 3+ years of experience in RTL Design with a strong background in IP and SOC integration, PADRING, segment clock gating, LINT checks and Design Compiler elaboration fixes. Having a good understanding of repeaters, power domains, verification testcases debug, RTL to GDSII workflow.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in RTL Design and SOC integration.
Location: Delhi, India
Experience: 4 yrs 4 mos
Skills
- Rtl Design
- Soc Integration
Career Highlights
- 3+ years of experience in RTL Design.
- Strong background in IP and SOC integration.
- Proficient in debugging verification testcases.
Work Experience
AMD
Silicon Design Engineer 2 (3 yrs 10 mos)
Co-Op (6 mos)
Maven Silicon
VLSI Design Intern (2 mos)
DRDO, Ministry of Defence, Govt. of India
Summer Trainee (1 mo)
Education
Master of Technology - M.Tech at Delhi Technological University (Formerly DCE)
Bachelor of Technology - B.Tech at Jaypee Institute Of Information Technology
Class XII at Ahlcon Public School, Delhi
Class X at Vishwa Bharati Public School, Noida