Nikhil Tiwari

Software Engineer

Delhi, India13 yrs 4 mos experience

Highly Stable

Key Highlights

Over 12 years of experience in ASIC/FPGA design.
Expertise in System on a Chip (SoC) integration.
Proficient in multiple design tools and methodologies.

Stackforce AI infers this person is a highly skilled ASIC/FPGA design engineer with extensive experience in infrastructure and system integration.

Contact

Skills

Core Skills

Axi

Other Skills

System memory management unit (SMMU)Generic interrupt controller (GIC)AMBA AHBMicroarchitectureVHDLVerilogPCB designOrCAD Capture CISAllegroOrcadRTL codingFPGAXilinx ISEAltera QuartusC

About

Currently working as part of infrastructure IP team with Qualcomm. With overall 12+ years of experience in ASIC/FPGA design with comprehensive knowledge of the design flow and tools.

Experience

13 yrs 4 mos

Total Experience

3 yrs 10 mos

Average Tenure

1 yr 11 mos

Current Experience

Qualcomm

Senior Staff Engineer

May 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India

System memory management unit (SMMU), Generic interrupt controller (GIC)

System memory management unit (SMMU)Generic interrupt controller (GIC)

Nxp semiconductors

3 roles

Principal Engineer

Apr 2022 – Jun 2024 · 2 yrs 2 mos

Staff Engineer

May 2020 – Mar 2022 · 1 yr 10 mos

AXI

Lead Design Engineer

Jul 2017 – May 2020 · 2 yrs 10 mos

AMP group (Automotive IP Design Team)

AXI

Stmicroelectronics

2 roles

Tech. Leader

Jul 2016 – Jun 2017 · 11 mos

AXI

Senior Design Engineer

Sep 2014 – Jun 2016 · 1 yr 9 mos

RTL design engineer, APG (Automotive Digital IP) group

AXI

Ittiam systems pvt ltd

2 roles

Senior Engineer

Promoted

Apr 2014 – Aug 2014 · 4 mos

Hardware Engineer in Multi-Media Systems group.
Responsibilities include -
1. Hardware (Design, Component selection, Generate ORCAD Schematics, Supervising & review of layout, Gerber generation from CAD (third party), Testing of assembled board)
2. FPGA RTL design (RTL architecture, Selection of FPGA (Xilinx, Lattice, Altera), RTL coding in Verilog/VHDL, Functional verification & Final testing on board).

Engineer

Jul 2012 – Mar 2014 · 1 yr 8 mos

Hardware Engineer in Multi-Media Systems group.
Responsibilities include -
1. Hardware (Design, Component selection, Generate ORCAD Schematics, Supervising & review of layout, Gerber generation from CAD (third party), Testing of assembled board)
2. FPGA RTL design (RTL architecture, Selection of FPGA (Xilinx, Lattice, Altera), RTL coding in Verilog/VHDL, Functional verification & Final testing on board).