Shailendra Dwivedi — Software Engineer
1. ASIC/SOC design verification experience: 9 years 2. vip development experience: 7 months ( UVM). 3 ASIC hardware security working experience: 6 years 4 CPU bring up from scratch in soc dv environment: 6 projects 5 Critical silicon bring up & silicon debug expert: 5 years
Stackforce AI infers this person is a highly skilled ASIC/SOC design verification engineer with a focus on hardware security.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 7 mos
Career Highlights
- 9 years of ASIC/SOC design verification experience.
- Expert in CPU bring up and silicon debug.
- Proficient in ASIC hardware security.
Work Experience
Qualcomm
Staff Design verification engineer (4 mos)
Senior Lead Design Verification Engineer (3 yrs 4 mos)
Senior Design Verification Engineer (3 yrs 10 mos)
MosChip
ASIC verification engineer (1 yr 5 mos)
Cadence Design Systems
SoC Solutions Engineer (2 yrs)
3ST Technologies
Design Verification Engineer - trainee (6 mos)
Tevatron Technologies Pvt. Ltd.
Digital Design Engineer-intern (VHDL & Verilog) (6 mos)
C-DAC, Mohali
VLSI design and implimentaion (2 mos)
Education
Bachelor of Technology (B.Tech.) at Malout Institute of Managment & Technology, Malout
S.S.C at Centre for Development and Advance Computing
at N.M. Jain senior secondary school, bharat nagar, Ludhiana
