Pavan M. — Director of Engineering
Engineering Leader | FPGA/ASIC/Embedded Systems | Motor Control | Aerospace Solutions | Navigation Engineering leader with proven experience in building high-performing teams from scratch and driving them to deliver results on time and with excellence. My career spans across ASIC, FPGA, and Embedded Systems, covering the full cycle of design, development, verification, and validation. Having strong experience in both pre-silicon and post-silicon. With strong expertise in Motor Control systems, GPS/GLONASS baseband receiver design, and aerospace-grade solutions, And Pre and post silicon validation for various ASICS, SoCs, FPGAs I bring hands-on technical leadership combined with experience in customer-focused, high-pressure project environments. Technical Expertise (Summary) FPGA/ASIC/SoCs/ACAP/Embedded Systems: End-to-end design, development, verification, and validation (pre- & post-silicon). Motor Control: Multi-axis control (up to 6) including PMSM/BLDC (FOC, sensorless, Hall/Encoder), sinusoidal & block commutation, stepper motors, and configurable DC fan controllers. Aerospace & Safety-Critical Systems: RTCA/DO-254 compliant design, verification, and validation; familiarity with DO-178B. Signal Processing: GPS & GLONASS baseband receiver development. Tools & Languages: Verilog, VHDL, C, TCL, Perl, MATLAB/Simulink; EDA tools (ModelSim, Synplicity, Libero, Quartus, Xilinx ISE). FPGA Platforms: AMD/Xilinx (Versal, Zynq, Ultrascale+, Spartan, Virtex, CoolRunner), , Actel (SmartFusion, Fusion, Igloo, ProASIC), Altera (Stratix, Cyclone, Max CPLD). Other Skills: Strong Board-level debugging, FPGA validation, version control (CVS, SVN),
Stackforce AI infers this person is a leader in Aerospace and Embedded Systems engineering with a focus on FPGA and ASIC technologies.
Location: Hyderabad, Telangana, India
Experience: 20 yrs 5 mos
Career Highlights
- Proven experience in building high-performing engineering teams.
- Expertise in Motor Control and aerospace-grade solutions.
- Strong background in pre-silicon and post-silicon validation.
Work Experience
AMD
Sr Manager (4 yrs 2 mos)
Xilinx
Engineering Manager (8 yrs 5 mos)
Actel now Microsemi SoC
Staff Engineer (4 yrs)
Accord Software & Systems
Systems Engineer (3 yrs 10 mos)
Education
Master of Technology - MTech at Birla Institute of Technology and Science, Pilani
B.Tech at Jawaharlal Nehru Technological University
Intermediate at Usha Junior College
B.Tech at Jawaharlal Nehru Technological University Hyderabad (JNTUH)