S

Sivarama Prasad Valluri

Product Engineer

Bengaluru, Karnataka, India20 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Verilog, SystemVerilog, and VHDL.
  • Proven track record in FPGA prototyping and verification.
  • Innovative in automating VHDL testbench generation.
Stackforce AI infers this person is a Semiconductor expert with strong FPGA and verification skills.

Contact

LinkedIn

Skills

Core Skills

VerilogFpgaVhdlCVerification

Other Skills

SystemVerilogSynplify ProModel CompilerVHDL TB generatorAutomationSystem CVerilog PLITest case creationTest plan creationMatlabEthernetTCLModelSimLogic SynthesisStatic Timing Analysis

About

Specialties: Languages : Expertise in Verilog, SystemVerilog,VHDL, VHDL-2008 Expertise in C, Perl, TCL Hands on Experience in C++ and System C Tools : Synthesis: Synplify Pro, XST, Quartus Simulators: ModelSim, VCS, Aldec Formal Verification: Formality High Level Synthesis: Synopsys Model Compiler

Experience

20 yrs 3 mos
Total Experience
6 yrs 9 mos
Average Tenure
11 yrs 5 mos
Current Experience

Nvidia

FPGA PROTOTYPING ENGINEER

Nov 2014 – Present · 11 yrs 5 mos · Bangalore

VerilogSystemVerilogVHDLFPGA

Synopsys

CAE

Oct 2008 – Oct 2014 · 6 yrs

  • Responsible for validating RTL related features in Synplify Pro/Premier tools which includes Verilog, - SystemVerilog, VHDL, and VHDL-2008
  • Responsible for validating C-Output Feature of Synphony Model Compiler
  • Responsible for creating proof of concept models for different wrappers(Verilog PLI, System C, Simulink Wrapper) of Synphony Model compiler C-Output
  • Taken initiative to create a VHDL TB generator to automate the VHDL TB generation process
  • Taken initiative to come-up with framework requirements for productivity improvements in multiple projects and implemented them
  • Derived the regression framework requirements for multiple features from the scratch and implemented them
VerilogSystemVerilogVHDLCSynplify ProModel Compiler+1

Hcl technologies

Lead Engineer

Nov 2005 – Sep 2008 · 2 yrs 10 mos

  • Worked on verification projects, involved in verification environment creation, test case creation, test plan creation.
  • Also involved in board testing for some time.
VerificationTest case creationTest plan creation

Education

Amrita School of Engineering

m.Tech — VLSI Design

Jan 2003 – Jan 2005

R.V.R & J.C College of Engineering, Guntur

B.Tech — Electrical and Electronics

Jan 1999 – Jan 2003

Sri Vivekananda Vidya Nikethan

Vignana Vihara, Gudilova

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