Jun 2013 – Aug 2016 · 3 yrs 2 mos · Greater Chennai Area

• LTE development on TI's platform
• The platform used for our development is TI's multicore dsp(TCI6614) based evaluation module. There are 4 DSP cores and an ARM core in our system. The clock frequency is upto 1.2GHz and the processor supports floating and fixed point formats. Since floating point format is supported receiver algorithms can be developed without losing much precision.
• In our architecture eNodeB transmit chain is running on Core 0, L2 on Core 1 ,eNodeB receive chain on core3. Similary on another evaluation module UE processing is ported. UE transmit chain is running on Core0,L2 on core 1 and UE receive chain on core 3.
• Multicore navigator module enables data transmission through the processor. It handles packet transmission and accelerator triggering. Many of the complex digital signal processing techniques are carried out using hardware accelerators. FFT, Turbo encoding and decoding, viterbi decoding can be carried out using accelerators. These accelerators accepts inputs in packet format.
• There are three levels of memory for the processor architecture. Each DSP core has its own level 1 program (L1P) and level 1 data (L1D) memory. Additionally, each Core has a local level 2 unified memory. Each of the local memories can be independently configured as memory-mapped SRAM, cache, or a combination of the two. There is a multicore shared memory which eliminates data transfers across cores.
• Works done
• eNodeB transmit chain implementation and testing.
• UE receive chain implementation.
• Code optimization