S

Sashank Katta

Product Engineer

Bengaluru, Karnataka, India13 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 11 years of experience in product and test engineering.
  • Expert in silicon debug and yield improvement.
  • Proficient in ATE program development and test optimization.
Stackforce AI infers this person is a Semiconductor Testing Specialist with extensive experience in ATE and product characterization.

Contact

Skills

Core Skills

TestingCharacterization

Other Skills

ATE program developmentADVANTEST platformtest time reductionDDR characterizationTest program developmentADVANTEST VERIGY 93Kyield enhancementDebuggingSoCEmbedded SystemsMatlabMixed SignalICLinuxSemiconductors

About

Product and Test Engineer (ATE) with an experience of 11+ years. Skilled in Smartest,V93k, T2k, Synopsis DC for DFT, C, and C++. Worked on silicon debug, yield improvement, test time, cost reduction and test program integration, I have also worked on individual modules like SCAN, AUX, DDR, USB3.

Experience

13 yrs 2 mos
Total Experience
4 yrs 4 mos
Average Tenure
6 yrs 9 mos
Current Experience

Intel corporation

Product Development Engineer

Aug 2019Present · 6 yrs 9 mos · Bangalore

Amd

Product Development Engineer

May 2017Aug 2019 · 2 yrs 3 mos · Singapore

Tessolve semiconductor pvt ltd (tessolvedts inc)

2 roles

Product Test Engineer

Apr 2016May 2017 · 1 yr 1 mo

  • ATE program development on ADVANTEST platform at Client location and helping in enchaining test time, covearge etc. 9G DDR characterization on controller interface for LPDDR3/4.
ATE program developmentADVANTEST platformtest time reductionDDR characterizationTestingCharacterization

Post silicon Validation Engineer

Mar 2013Apr 2016 · 3 yrs 1 mo

  • Developing test programs on ADVANTEST VERIGY 93K ATE platform for SOC (System on Chip) devices as well as Test Program Optimization involving yield enhancement and test time reduction. Good in Semiconductor Product Test and Characterization Engineering. Currently handling DDR characterization.
Test program developmentADVANTEST VERIGY 93Kyield enhancementtest time reductionDDR characterizationTesting+1

Education

SCIENT INST/JNTU UNIV

B-TECH — E.I.E

Jan 2008Jan 2012

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