K

kalyan kumar o

DevOps Engineer

Bengaluru, Karnataka, India16 yrs 4 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC design and implementation.
  • Proven track record in optimizing CPU performance.
  • Strong leadership in managing engineering teams.
Stackforce AI infers this person is a Semiconductor ASIC design expert with a focus on CPU architecture.

Contact

LinkedIn

Skills

Core Skills

AsicVlsi

Other Skills

CPU designRTL modificationssynthesisLECCLPPDPhysical designARM CPU coresConstraintsECOsPPA improvementDesignRTL designDAC verificationMemory BIST

Experience

16 yrs 4 mos
Total Experience
9 yrs
Average Tenure
1 yr 7 mos
Current Experience

Meta

2 roles

Asic Implementation Manager

Promoted

Nov 2025 – Present · 5 mos · Hybrid

Asic Implementation Engineer

Aug 2024 – Oct 2025 · 1 yr 2 mos · Hybrid

Qualcomm

6 roles

Sr.Staff Engineer / Manager

Promoted

Dec 2021 – Present · 4 yrs 4 mos · Bengaluru, Karnataka, India

  • Worked on various power and performance CPU cores . Delivered Area efficient, power optimized CPU cores that deliver best in class performance.
  • Lead teams of 7-8 members to deliver best in class synthesized netlists for full CPU sub system
  • Owned various aspects of CPU design - RTL modifications, synthesis, LEC, CLP, PD for various cores
CPU designRTL modificationssynthesisLECCLPPD+2

Staff Engineer

Dec 2016 – Nov 2021 · 4 yrs 11 mos · Bengaluru, Karnataka, India

  • Worked on physical design of power efficient ARM CPU cores
Physical designARM CPU coresASIC

Sr.Lead Engineer

Aug 2014 – Nov 2016 · 2 yrs 3 mos · Bengaluru, Karnataka, India

  • Worked on Synthesis for various CPU cores . Owned constraints, ECOs for multiple tapeouts . Worked on various methodologies for improving PPA of CPU cores
SynthesisConstraintsECOsPPA improvementASIC

Senior Engineer

Promoted

Aug 2012 – Jul 2014 · 1 yr 11 mos · Bengaluru, Karnataka, India

  • Worked on design of Video pre-fetch engine , owned synthesis, constraints, LEC and CLP for entire Video Core
DesignSynthesisLECCLPASIC

Engineer

Aug 2009 – Jul 2012 · 2 yrs 11 mos · Bengaluru, Karnataka, India

  • Worked on RTL design for top level mode muxing , DAC verification and Memory bist
RTL designDAC verificationMemory BISTASIC

Intern

Aug 2008 – Jul 2009 · 11 mos · Bengaluru, Karnataka, India

  • Worked on full chip synthesis and constraints
Full chip synthesisConstraints

Education

Birla Institute of Technology and Science, Pilani

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