RAJISHA E.R — Product Engineer

• Tool Expertise: Synopsis Tools : DFT compiler, BSD Compiler, Tetramax, Memory Compiler , Integrator, Builder, Verifier, Silicon Debugger, Formality, VCS. Cadence Tools : RTL Compiler, Encounter Test, NCSim, Conformal LEC, Encounter Timing System. Mentor Tools : Tessent FastScan/TestKompress, MBIST/BSCAN tools, QuestaSim Another Tools : Vector translation tool VTRAN, MATLAB • Core Expertise:  Proficient in DFT planning, Implementation and evaluation.  Implemented DFT schemes like SCAN, SCAN Compression, Boundary SCAN, Memory BIST, JTAG and DDR BIST.  Integrated commercial ATPG tool to perform Stuck-at, Atspeed and Iddq fault testing and generated high quality test patterns.  Proficient in Mbist/Bscan Insertion and Proficient in Tessent MBIST flow and Synopsys STAR Memory System flow.  Proficient in Memory generation using Synopsys Memory compiler.  Experience in DDR BIST Implementation and Simulation.  Proficient in Logic equivalence checking/Formal verification.  Experience in developing test benches and simulation in RTL/GATE/SDF.  Gook knowledge in logic design in Verilog and has experience in synthesis, static timing analysis.  Experience in vector conversion from verilog VCD/EVCD files to WGL or STIL with read back validation flow using VTRAN. • Programming Scripting Languages : Verilog, PERL and TCL.

Stackforce AI infers this person is a DFT and testing expert in the VLSI industry.

Location: Bengaluru, Karnataka, India

Experience: 15 yrs