Kapil Raj Dangeti

Software Engineer

Andhra Pradesh, India19 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Senior Design Engineer with extensive ASIC experience
Expert in VLSI design and physical design methodologies
Proficient in RTL design and static timing analysis

Stackforce AI infers this person is a VLSI Design Engineer specializing in ASIC and SoC development.

Contact

Skills

Core Skills

AsicVlsi

Other Skills

SoCEDAPhysical DesignRTL designDRCVHDLStatic Timing AnalysisCircuit DesignVerilogFloorplanningTCLTiming Closure

Experience

19 yrs 1 mo

Total Experience

9 yrs 6 mos

Average Tenure

14 yrs

Current Experience

Amd

Senior Design Engineer

Apr 2012 – Present · 14 yrs

ASICSoCEDAPhysical DesignRTL designDRC+8

Synopsys india pvt. ltd

Sr. Engineer

Feb 2007 – Mar 2012 · 5 yrs 1 mo

Education

CDAC Noida

M.Tech — VSLI Design

Jan 2004 – Jan 2006

Stackforce found 100+ more professionals with Asic & Vlsi

Explore similar profiles based on matching skills and experience

Rahul Chaturvedi

Design Engineering Manager

at AMD

Bengaluru, India21 yrs 2 mos exp

Functional VerificationSoCIP/SOCSOC Verification

Udit Kumar

Sr. Manager Silicon Design

at AMD

Noida, India21 yrs 7 mos exp

ASICFunctional Verification

Pankaj Verma

Design Verification Lead

at Accenture

Bengaluru, India25 yrs 2 mos exp

Functional Verification

Manjunatha Vadiarillat

at Synopsys

Hyderabad, India25 yrs 7 mos exp

Gaurav Goyal

Technical Director

at NXP Semiconductors

Bengaluru, India17 yrs 8 mos exp

Siddartha Papineni

Formal Verification Lead

at Synopsys Inc

Mountain View, United States14 yrs 7 mos exp

Formal VerificationQuality Assurance

RAJISHA E.R

DFT Engineer

at Intel Corporation

Bengaluru, India15 yrs exp

Automatic Test EquipmentDebuggingSimulationsLogic BISTBoundary Scan

Mohanasundaram S

Senior Department Manager

at MediaTek

Bengaluru, India19 yrs 3 mos exp

DFT