Jul 2016 – Dec 2021 · 5 yrs 5 mos · Bengaluru, Karnataka, India

• I am working as ATE Test Engineer with 3+ years of experience on Verigy 93k & INTEL CMT Tester platform. Expert in ATE Test Program development on Digital and Mixed signal devices, Debug, Test Method developments, Test time Reduction, Test Content Generation
•  Expert in developing test methods in C, C++ languages.
•  Expert in developing test program for multisite Loadboards ( 4 sites, 8sites).
•  Debugging test vectors for Digital & Analog devices on ATE platform (Verigy 93K) and also bench tools like Oscilloscope and function generator etc…
•  Characterizing the device by testing in different PVT conditions like Process variations (Corner Lots), Voltage and Temperature.
•  Feasibility study for new projects based on device spec vs available ATE test resources to meet required condition to validating the device.
•  Pattern conversion from VCD, EVCD, WGL to tester supportive V93K BIN format using vTran script.
•  Knowledge on DFT concepts : ATPG, JTAG Boundary Scan & BIST
•  Onsite Production/Program release experience at Taiwan, South Korea, Malaysia.
• Worked on Coffeelake 8+2 Processor 10nm Product (CMT Platform) as CW Engineer in INTEL
•  Objective:
• Support on Test Program Integration, EQA/PHM RV, CSE & Module development.
•  Roles and Responsibilities:
•  Class Test Program Integration, Mini/Full Correlation Submission, WTL and Data Analysis, Release Notes & WP Generation.
•  TPI Base Modules development on CFL 8+2.
•  TTR Test Program development on FUNC Module.
•  EQA/PHM Rejects Debug & Disposition.
•  CSE TP development, Rejects Validation & disposition.
•  TVPV STIL Pattern Generation and conversion to pobj format
•  Knowledge on DIE Recovery.
• Software Exposure:
•  TPIE, TRACE, AQUA, MOLE, JUMP, AURA, TVPV, TPRSLite, DVS workspace, PATVAL, DEDC