Feb 2021 – Nov 2023 · 2 yrs 9 mos · Bengaluru Area, India

• Role: Full Chip Timing Lead and Clocking Manager
• Responsibilities:
• Managed a team of 7 people with expertise in timing and custom clocking work.
• Drive Full Chip Timing to closure (manage the schedule and lead the team technically)
• Huge chip of 400mm2 with 5 power domain and clock frequency >2GHz
• Managed and technically led all STA and custom clocking activities for the SoC.
• Technical lead of all timing activities on the SoC ranging from constraints management, interface with architects, timing and review closure.
• Drive and execute all custom clocking activities on the SoC
• Responsible for all custom clocking working on SoC including physical implementation, spice simulation for various variation impacts on clock and margining it in timing

Nov 2018 – Nov 2023 · 5 yrs · Bengaluru Area, India

• APR and FEV Lead:
• Was leading 10 blocks in a networking ASIC from placement to GDS.
• Was executing a subsystem with 4M total instance count from placement to GDS.
• Was responsible for streamlining FEV flow for the whole SoC and technically leading all the FEV activities on the SoC.
• STA Lead
• Owned SoC functional mode timing and overall constraints methodology for the a networking project
• Actively worked in streamlining a new flow to take the design from RTL to GDS
• Responsible for understanding the architecture from SoC and understand it completely from timing perspective.
• Technical lead for all STA activities on the project.
• Clocking Lead
• Leading all clocking related activities on a server project
• Responsibility included providing technical guidance to clocking team on all custom clocking work for clocks running more than 2GHz, ensuring clock spec (skew, tran etc) is met without burining too much area in SoC
• Responsible for all jitter and DCD simulation and computation activities for all the clocks in SoC. This included discussing the methodology of doing so and trying to improve the same.
• Interface with clock micro-architect to understand all clock spec and architectural requirements and use the same for implementation.

May 2017 – Nov 2018 · 1 yr 6 mos

• Implementation of a 40ULP chip used in medical devices
• Responsibilities include
• Lead all back end efforts for the device which includes synthesis, STA, layout and ATPG
• Tap controller integration in the device
• Write the RTL code for dft hookup at device for daisy chaining etc.
• Synthesis, STA and CLP for a design with multiple power domains
• Layout of a couple of digital blocks
• Chip lead and SoC Layout for a 16nm 1.6GHz buffer chip in collaboration with IBM
• Responsibilities Include:
• Lead all backend efforts which includes synthesis, layout and STA
• Customer interface for backend
• Top level layout of the SOC
• Manage a team of 6

Sep 2016 – Apr 2017 · 7 mos

• Layout Block lead for a 16nm chip:
• Leading all the block level layout activities of a 16nm device .t. There are a total of 10 blocks in the device including complex PCIE Gen4 SerDes. Technically driving CTS and placement methodologies of these complex blocks apart from project status management
• Feasibilities on couple of digital IPs to streamline the design and flow. Since this is the first 16nm chip of the company a lot of trials are required.
• Also leading the padring design efforts of this project and ramping up a junior resource on the same.

Oct 2015 – Sep 2016 · 11 mos

• 1. Did complete RTL to GDS for a digital IP which is a switch by design (PCIe Switch). This included taking in the RTL, synthesizing it, inserting test logic, do layout - timing and physical, perform STA for sign off.
• 2. Did PnR in INNOVUS and helped to tune the flow to improve the QOR out of the tool. This is a new tool and hence lot of small tunings required to improve the QOR and correlation with STA sign off tool.

Jun 2015 – Sep 2015 · 3 mos

• Device STA for a 28nm chip
• Was the device level STA lead for the chip
• Was responsible for doing functional and scan_shift mode STA for the whole device including leading the STA for other modes.
• Owned the constraints management and STA setup for the whole device thus enabling block owners to just run STA and not bother about STA setup and constraints for their blocks.

Jul 2014 – Jun 2015 · 11 mos

• Implementation of 28nm chip:
• Designed and implemented the padring for the whole device
• Synthesized device RTL and ran Conformal LEC between RTL and post-layout netlist.
• Implemented many functional ECOs at device level.
• Designed the DFT strategy for the device including test clock matrix, scan daisy chaining, DFT hookup RTL etc.
• Owned the bump and ball worksheet and ball maps for the device.
• Was responsible for doing device level STA for scan_shift and rambist modes. Provided constraints from top to block level to ensure speedy timing closure of the device for test modes.

Feb 2011 – Jun 2014 · 3 yrs 4 mos

• IMPLEMENTATION of High Speed Designs in 40nm and 28nm
• Responsible for synthesis and STA for high speed DDR2/3/4 interface (upto 2.67G data rate) . Developed a set of complex timing scripts to report various timing checks (like skew, transition, logic depth etc) required for DDR interface. Helped in creating tighter constraints for the interface based on failures seen in lab.
• Implemented a very complex ECO in DDR design thus preventing a potential re-spin of the design. This was typically designer’s responsibility to implement but volunteered to implement the same due to the complexity. Was awarded spotlight by my manager for doing the above ECO and adding value to the project.
• Helped in timely closure of DDR interface where the design had to be closed for timing twice due to bad constraints provided by vendor. Was awarded spotlight award from the Mixed Signal Manager for the excellent support.
• Mentored junior resource on high speed interfaces (DDR, Flash).
• Leading a group of engineers implementing DDR and Flash Interfaces across the company.
• Wrote a technical paper of DDR PHY Implementation using SNPS IP for SNUG. Paper was accepted but was not allowed to present by company management due to confidentiality issues.
• Participated in SNPS DDR IP postmortem with SNPS to change their design to ease timing closure for future projects.
• Worked on timing closure of SerDes interface. Also worked on improving the correlation between synthesis and layout by fine tuning the resistance/capacitance scaling factor in synthesis.