Rathina Balan Thalaiappan

CEO

Bengaluru, Karnataka, India24 yrs 2 mos experience

Highly StableAI Enabled

Key Highlights

Expert in AI supercompute silicon and software development.
Proven track record in system software and firmware management.
Leadership in founding and expanding tech teams.

Stackforce AI infers this person is a high-level architect in AI and embedded systems.

Contact

Skills

Core Skills

Ai PipelinesPlatform SoftwareAi Supercompute SiliconAi Software StackRisc-vSecure Boot SequencePower Management Unit FirmwareCpu ArchitecturesX86 Emulation PlatformDevice DriversVirtual Prototype Models

Other Skills

IntegrationPortingBring-upKernel-level performanceCI/CD and analysisSystolic arraysIn-memory computingCustom scale-out IP modelsChiplet managementRISC-V emulatorPower management algorithmsSMP issuesBluetooth integrationConditional access stackSerDes

About

An accomplished System Software/Firmware Architect with extensive experience across various tech companies, including Krutrim SI Designs, Bodhi Computing, Intel, Infineon, and Highgate Worldwide. Expertise spans AI supercompute silicon and software development, RISC-V based CPU systems, power management for Intel Edge devices, and the integration of x86 architecture in modems. Proven track record in developing and managing system software, firmware, and device drivers across multiple platforms and architectures, with notable achievements in AI data flow architectures, secure boot sequences, power management firmware, and dual OS environments. Successfully performed 30+ silicon power ons. Demonstrated leadership in founding teams, team expansions, and cross-functional collaborations, contributing to significant advancements in technology and innovation.

Experience

24 yrs 2 mos

Total Experience

5 yrs 10 mos

Average Tenure

7 mos

Current Experience

Relu technologies private limited

Chief Executive Officer

Oct 2025 – Present · 7 mos · India

I lead the strategic vision and execution of modular AI and platform software that unify silicon, cloud, and edge. With 24 years of experience and 18+ major system bring-ups across consumer, mobile, automotive, server, and networking domains, I drive scalable pipelines from training and fine-tuning to edge deployment—anchored in platform integration, porting, and bring-up expertise.
FOCUS AREAS
AI pipelines: Transformer training, fine-tuning, and quantization (FP32, INT8) integrated with edge inference and reproducible deployment.
Platform software: UEFI, bootloaders, BSPs, device drivers, and system firmware across RISC-V, ARM, and x86.
Integration, porting, bring-up: Multi-core prototypes, CPU migrations, and server workload enablement on RISC-V.
Virtual prototyping: QEMU, Simics, SystemC, HAPS for pre-silicon modeling & development; custom IP and interconnect models (CPU-SS, AI IP, PER-SS).
Kernel-level performance: Parallel programming across GPUs, TPUs, and custom silicon; silicon-aware optimization for edge and server targets.
CI/CD and analysis: Automated build/triage pipelines, core-dump analysis frameworks, MTBF dashboards for faster stabilization.

AI pipelinesPlatform softwareIntegrationPortingBring-upKernel-level performance+1

Krutrim si designs

Fellow - System and Core Software

Aug 2023 – Sep 2025 · 2 yrs 1 mo

Architected system software and firmware for AI supercompute silicon.
Defined AI software stack for data flow architecture using systolic arrays and in-memory computing.
Developed custom scale-out IP models for routing topology exploration.
Led the design of AI supercompute PreSi prototypes.

AI supercompute siliconAI software stackSystolic arraysIn-memory computingCustom scale-out IP models

Bodhi computing

Founding Member

Apr 2023 – Jul 2023 · 3 mos · Bengaluru, Karnataka, India

Architected a RISC-V based server-grade CPU system with Tenstorrent collaboration.
Defined chiplet management scheme within System-on-Package (SOP).
Designed secure boot sequence for integrated system.
Developed RISC-V emulator for essential server workloads, presented at the RISC-V conference in Bangalore.

RISC-VChiplet managementSecure boot sequenceRISC-V emulator

Intel corporation

2 roles

Principal Engineer

Apr 2019 – Mar 2023 · 3 yrs 11 mos

Established and expanded a team dedicated to Power Management Unit (punit) firmware.
Developed power management algorithms for Intel Edge devices, integrating features from Client and Server product lines.

Power Management Unit firmwarePower management algorithms

Senior Staff Engineer

Feb 2011 – Apr 2019 · 8 yrs 2 mos

Worked across multiple CPU architectures: ARM Cortex-A/R/M series, ARC, Xtensa, x86, RISC-V.
Addressed SMP issues on PreSi platforms and supported para-virtualization efforts.
Co-developed x86 emulation platform and integrated x86/SMP support in ThreadX.
Developed automated triaging system for crash and system log data, increasing MTBF.

CPU architecturesSMP issuesx86 emulation platform

Infineon

Staff Engineer

Oct 2003 – Feb 2011 · 7 yrs 4 mos

Designed device drivers for dual-core AP-CP architecture on Symbian OS.
Created virtual prototype models for modem IPs and companion devices.
Developed the APOXI Application Framework and supported Bluetooth integration.
Co-led the Modem Graphics team, delivering projects for Samsung, LG, and Nokia.
Developed hardware accelerator codec drivers and framework for Hantro IP.
Established Core Drivers team, managing key Modem system IP drivers and CPU subsystems.

Device driversVirtual prototype modelsBluetooth integration

Highgate worldwide and co.

Senior Software Engineer

Jan 2001 – Jan 2003 · 2 yrs

Developed device drivers and conditional access stack for CI and smartcard-based systems in set-top boxes.
Enhanced user experience with data caching and developing drivers for various peripherals.
Enabled remote debugging through a proxy module for the STi Microconnect (JTAG emulator).
Pioneered adoption of eCOS operating system and Java Virtual Machine in set-top boxes.

Device driversConditional access stack