Swapnil Sourav

Product Manager

Bengaluru, Karnataka, India9 yrs 6 mos experience
Highly Stable

Key Highlights

  • Over 10 years of experience in EDA design environments.
  • Expertise in automation and methodology development.
  • Proficient in Cadence Virtuoso and physical verification tools.
Stackforce AI infers this person is a Semiconductor Engineering expert with a strong focus on CAD and EDA tools.

Contact

Skills

Core Skills

Computer-aided Design (cad)Semiconductor EngineeringAnalog Design

Other Skills

SKILLPythonPerlUNIXTCLCadence VirtuosoCalibreStarRCFineSimPrimeSimProblem SolvingAnalog Circuit DesignLayout DesignLicense ManagementCAD Tools

About

I am currently working as a Principal Engineer in the CAD domain at SanDisk, with over 10 years of experience in developing and enhancing EDA design environments, focusing on NAND, Flash Memory, Analog and Mixed-Signal CAD flows. My expertise spans across automation, methodology development, and tool integration to improve design efficiency and verification accuracy. I have Expert level proficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL. I have Expertise in Virtuoso suite of tools and Analog Design environment (finesim/PrimeSim) Solid understanding of Calibre Physical Verification decks(SVRF) and ICV LVS decks with hands-n experience in integrating various PV flows in CAD environment. Solid experience in Layout Automation and Utilities development in Cadence SKILL/SKILL++. Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substrate noise analysis. My Responsibilities include testing, validation, customer support and new tool/methods evaluations, development of methods and procedures for quality improvement, automation of deck/techFiles generation and validation. Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors. Experience with physical verification tools for DRC, LVS and parasitic extraction, Calibre, starRC, ICV etc is plus. Working knowledge of revision control software (Git, Perforce, Synchronicity, etc) Ensuring the operation and support within the CAD for layout and circuit designers worldwide.

Experience

9 yrs 6 mos
Total Experience
2 yrs 3 mos
Average Tenure
5 mos
Current Experience

Sandisk

Principal Engineer

Nov 2025Present · 5 mos · Bengaluru, Karnataka, India · Hybrid

  • I am currently working as a Principal Engineer in the CAD domain at SanDisk, with over 10 years of experience in developing and enhancing EDA design environments, focusing on Analog and Mixed-Signal CAD flows. My expertise spans across automation, methodology development, and tool integration to improve design efficiency and verification accuracy.
  • I have strong proficiency in scripting and programming using SKILL, Python, Perl, UNIX shell, and TCL, with deep expertise in the Cadence Virtuoso suite and analog design environments such as FineSim and PrimeSim. My work includes development and validation of physical verification (PV) tools and flows—covering DRC, LVS, parasitic extraction, EM/IR drop, and substrate noise analysis—along with automation of tech file and deck generation processes.
  • I also have hands-on experience with Calibre (SVRF/TVF) and ICV decks, as well as layout automation and utilities development using SKILL/SKILL++. Additionally, I support global design teams by providing CAD methodologies, testing and validating new tools, and ensuring seamless operation across layout and circuit design teams worldwide. I am proficient in using version control systems like Git, Perforce, and Synchronicity for efficient flow management and collaboration.
  • Technical Skills: Cadence SKILL, StarRC, Totem. Calibre SVRF/TVF, Python, Shell Scripting.
SKILLPythonPerlUNIXTCLCadence Virtuoso+6

Siliconauto

Staff Engineer CAD

Dec 2024Nov 2025 · 11 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

Senior Design Automation Engineer

Jul 2018Nov 2024 · 6 yrs 4 mos · Bengaluru, Karnataka, India · On-site

Computer-Aided Design (CAD)Semiconductor Engineering

Elveego circuits

Member Of Technical Staff

Sep 2017Jul 2018 · 10 mos · Bengaluru Area, India

  • Analog Circuit and Custom Layout Design to execute Full Chip, Block and sub-block level from circuit schematics.
  • Extensive analog design experience in Analog circuits: ADC/DAC, LDOs, PLLs, Crystal Oscillators, temperature Sensors Hands-on experience in analog full custom design, detailed layout judgment and supervision capabilities Knowledge of SoC development
  • Independent Circuit and Layout of various Analog, Mixed Signal and RF blocks and sub-blocks of PLLs, CDRs, LVDS, HDMI, Serial I/Os, Filters, Data Converters and other building blocks.
  • Work independently, collaborating with Project Manager/Leader and design engineers.
  • Responsible for the timely execution as well as overall physical design quality of the implemented circuits.
  • Follow the Project Execution Plan, Project Schedule, Work Assignment and EDA tool usage plan.
  • Mentor and Guide Junior members of the team.
Problem SolvingAnalog Design

Stealth startup

Circuit and Layout Design Engineer

Aug 2016Aug 2017 · 1 yr · Bangalore

  • Layout Designing in Analog and Memory layout leaf cells designing.
  • Working Experience in CMOS based 6T SRAM memory design and Layout, STD cell design.
  • Strong debug and problem solving Skills for DRC, LVS checks,DRC Plus etc., at Top Level
  • Designing of ADCs/DACs, Memories like MRAM, PCRAM etc.
  • Knowledge on FinFET technology at different technology nodes.
  • Circuit Designing in Differential Amplifiers and its robustness
Problem Solving

Education

Birla Institute of Technology, Mesra

Master of Technology - MTech — ELECTRONICS AND COMMUNICATION ENGINEERING

Jan 2014Jan 2016

Biju Patnaik University of Technology, Odisha

Bachelor of Technology (B.Tech.)

Jan 2009Jan 2013

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