Amr Adel

Software Engineer

Cairo, Egypt6 yrs 3 mos experience

Key Highlights

Expert in ASIC backend design for SoC targeting wireless communication.
Proficient in RISC-V processor design and DSP implementation.
Strong background in high-speed CNN accelerator design on FPGA.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on ASIC design and digital signal processing.

Contact

Skills

Core Skills

System On A Chip (soc)Risc-vDigital Signal ProcessingPhysical DesignHigh-speed Cnn Accelerator

Other Skills

MatlabVerilogPhysical VerificationPerlStatic Timing AnalysisRTL DesignSystemVerilogVCSClock Tree SynthesisFloorplanningTiming ClosureLayout Versus Schematic (LVS)Design Rule Checking (DRC)TimingSynopsys Design Compiler

About

Electronics and communications engineer with a deep interest in digital design, software development, and A.I I create and share training materials for VLSI, DSP, RISC-V on Linkedin Feel free to contact me anytime if you have any questions, requests, suggestions, etc For anonymous feedback : https://whispa.link/amradelm

Experience

6 yrs 3 mos

Total Experience

1 yr 7 mos

Average Tenure

1 yr 4 mos

Current Experience

Startup

Senior PnR Engineer

Dec 2024 – Present · 1 yr 4 mos · Cairo, Egypt · On-site

Working as ASIC backend engineer for SoC Designs targeting wireless communication chips using Cadence toolchain and Siemens Calibre.

System on a Chip (SoC)

Confidential

Digital Design and PnR Engineer

Jul 2023 – Dec 2024 · 1 yr 5 mos

Focusing on designing RISC-V processors with M extension and privileged architecture.
Working with DSP team to implement DSP blocks for wireless communication such as FFT, Viterbi decoders, and digital filters.
Create Matlab models for wireless communication systems (PSK modulation, channel coding, interleavers, frame sync, etc)
Providing expert consultancy for ASIC SoC backend design, ensuring efficient and high-performance designs.
Building new CAD flow for digital team.

MatlabVerilogRISC-VDigital Signal Processing

Si-vision

2 roles

ASIC R&D Engineer

Feb 2023 – Jul 2023 · 5 mos · Cairo, Egypt · On-site

Handle PnR CAD
R&D for new topics/tools/flow
Supporting critical challenges in running projects

ASIC Physical Design Engineer

Nov 2020 – Jan 2023 · 2 yrs 2 mos · Cairo, Egypt · On-site

Work as a contractor for Synopsys on multiple IPs: DDR PHY IP, DDR CTRL IP, DDR Subsystem Integration, HBM IP, and Bluetooth Low Energy IP, on multiple tech nodes from 40nm down to 5nm.

Physical VerificationPerlPhysical Design

Mentor graphics

3 roles

Hardware Design Engineer Intern

Aug 2020 – Sep 2020 · 1 mo

Building an SoC on Altera FPGA using an embedded processor, DMA, and SATA IPs

Design of High-Speed CNN Accelerator on FPGA | Graduation Project

Sep 2019 – Aug 2020 · 11 mos

Design of high-speed accelerator of Squeeze-Net convolutional neural network architecture on Xilinx Virtex-7 FPGA. Sponsered by Mentor Graphics, One Lab, and ASRT.

Static Timing AnalysisRTL DesignHigh-Speed CNN Accelerator