Jun 2019 – Jan 2022 · 2 yrs 7 mos · Redmond, Washington, United States

• Working as Systems Engineer on Intel and AMD Compute servers, focussing on system level architecture, system requirements, integration guides, hw level security + threat models and validation during development (EV/DV/PV).
• Created a streamlined strategy for entry/exit criteria during product development for AMD Genoa CPUs, DDR5, PCIe Gen 5. This resulted in a clean traceable metric to gauge the progress of individual development phases (EV/DV/PV)
• Built and implemented HW security requirements and threat models, providing full coverage matrix for future Azure products. Collaborated with cross functional teams to provide scenario based system level threats and mitigations.
• Built automated at-scale server integration test framework using azcli, python, kusto, for simulating customer level stress. This identified hard to find failures (<1%) early on and be rectified before GA release of new products.
• Implemented full data pipeline + kNN clustering model to enable data driven analysis of failures seen in the field. This provided automated Root cause analysis in ~70% of cases and identified HW issues plaguing the azure services.

Feb 2016 – May 2019 · 3 yrs 3 mos · San Francisco Bay Area

• Worked as testing lead on the HW integration and validation testing on multiple generations of MacBooks and iMacs. Implemented a full data pipeline using Python, SQL, R, Tableau to analyze and forecast risk ramp readiness for Macs.
• Working with cross functional teams at Apple, defined and implemented the system usage metrics. This is used to highlight risk items and make recommendations to execs for ramping production before ship release of new Macs.
• Collaborated with marketing teams to make a case of highlighting the fastest SSD feature in a Mac, and how it elevates the product from rest, resulting in first ever mention of SSD speeds during any Mac reveal keynote.
• Built automated Mac integration testing using python, Django and RabbitMQ based framework for automated deployment of tests on 500+ Macs using centralized server, resulting in shortening of total testing time by ~50%.
• Automated real time analysis of big data generated from integration testing using Python, SQL and Tableau, providing live insights, automated triages and flagging HW issues, resulting in increased efficiency of system testing.
• Implemented machine learning kNN clustering model to enable data driven analysis of HW reliability. This predicted system failures early on, enabling the system team to take corrective actions during the prototyping phase.

Jul 2011 – Feb 2016 · 4 yrs 7 mos

• Part of core technology development team of the recently announced 3D X-Point Memory by Intel/Micron.
• Worked with Agrate Brianza wafer fab for scaling and technology transfer of 3D X-Point.
• Discovered and characterized novel fail modes on 3D X-Point to accelerate the definition of cell stack.
• Discovered and provided an analytical model for a new physical mechanism pertaining to this technology. Filed a disclosure to use on the product and provided a performance boost.
• Collaborated with different teams to define and implement wafer level test flow for 3D X-Point memory.
• Driving the ongoing process integration for cell stack of 3D X-Point by defining highly accelerated life tests (HALT) for various failure modes and providing the feedback to accelerate the development of cell stack.

Jul 2011 – Apr 2012 · 9 mos

• Part of reliability engineering team of the consumer and enterprise class 20nm planar NAND SSDs.
• Implemented the automated test routines to evaluate accelerated life tests for read failures on 20nm planar NAND.
• Designed novel experiments to provide analytical model and knowledge building of read failure mechanism.
• Performed reliability analysis of read failure mechanism to achieve high endurance 20nm planar SSD.
• Managed long term experiments (>1 year) to provide accurate assessment of retention failure over SSD life.

Aug 2009 – May 2011 · 1 yr 9 mos · Gainesville, Florida Area

• Collaborated with Georgia Tech to simulate, fabricate and test novel airgap interconnects.
• Worked on fabrication of high aspect ratio waveguide (40:1) using micro stereo lithography technique.

May 2008 – Jul 2008 · 2 mos · Erlangen, Germany

• Designed a mass flow rate controller with 5x faster settling time compared to commercially available products.
• The design was later approved for commercial production by FMP Technology.