Jul 2021 – Present · 4 yrs 9 mos

Aug 2014 – Jun 2021 · 6 yrs 10 mos

• Display Compliance Validation and Development
• Process to Certify Intel Platforms for DP and HDMI Displays in accordance to VESA (Video Electronics Standards Association) Protocol Suite from certified ATC’s.
• Responsibilities Include:
• Developing and Validating Compliance Test procedures Defined by VESA Protocol Suite for HDMI and DP Display Protocols
• Getting Platforms Certified by VESA by running them in VESA Certified ATC’s for HDMI and DP displays
• Compliance tests for HDMI include: HDMI 1.4 and 2.0 protocol, S3d Testing, HDCP 2.0 and 2.0 testing, Color features, 4kx2k.
• Compliance tests for DP include: DP Link, DP MST, MST 1.2, DP HDCP, DP Audio.
• Executing and planning test cases on the Intel Graphics Driver for Compliance related Issues.
• Debugging Compliance related issues found in Intel Graphics Driver
• Feature Owner for Compliance HDCP validation and Developing test cases for Validation
• Feature Owner for Compliance MIPI Validation
• HDCP Validation and Automation Framework
• This project includes End to End Performance Validation of the HDCP Protocol on the Intel Graphics Driver and Platforms. Validation of the new HDCP2.2 Protocol on HDMI 2.0 displays and developing Automaton suite for HDCP validation
• Responsibilities Include:
• Development of HDCP2.2 test cases for Functional validation
• Planning test cases for the Graphics Driver validation for the impact analysis due to change in other components
• Worked on Implementing LSPCON(Level Shifter Protocol Convertor) on Intel Platforms to driver HDMI 2.0 and HDCP 2.2 Functionality
• Developing a Automation test suite for HDCP end to End Validation
• Debugging Issues on HDCP and LSPCON Bugs

Jan 2014 – Jul 2014 · 6 mos

• Post Silicon Validation Tools
• a. Aubload: This tool is used for Validating Hardware Functionality using the I/O Access Drivers. Specifically includes validation the Display Hardware Pipeline, Frame buffers, Power Management Registers, 3D and Media Components.
• Responsibilities Include
• As a part of Development , Developed modules for Display, Media, 3D, Audio and Power Management
• Debugging and Fixing Display code related issues
• Implementing New Display and Audio Features
• b. VISA: The tool specifically used for Validating Power Management related registers which include Display and Graphics Unit. This Tool simulates all the registers in these units and validation team performs Functional validation using this tool by running in Fulsim environment. Responsibilities Include
• Integrating and maintaining HW specification XML files generated by the RTL Engineers
• Validating the Functionality of the tool by taking the test cases from the Validation Engineers
• Debugging and fixing issues.
• Implementing new features based on the Functionality change in the new upcoming Platforms

Feb 2013 – Sep 2014 · 1 yr 7 mos

• Digital Dsiplay Measurement Unit
• This project aimed at developing a Display simulation card where it can mimic HDMI and DP Displays. The card will mimic the displays by loading the EDID’s without having real displays connected and give the full functionality of display for the validation engineers to validate the features of Panel and Display Protocols.
• Responsibilities Include:
• a. Developing and maintaining USB Driver and Firmware, which Atmel Microcontroller uses to communicate to the Target systems and the Display Daughter card.
• b. Developing and Maintaining Framework to run the test cases and to access the functionality and registers of the card.
• c. Integrating test Cases into the framework to Validate the features of Displays and Display Protocols
• d. Implemented HDMI Features like Hotplug/Unplug, Frame Capture, CRC Capture, Lid Switch testing, HDCP , Validate during Different Power states, YUV Color Format testing, Support for Different Color Formats.
• e. Worked Closely with FPGA team to implement the Changes and development related to FPGA Programming

Jul 2012 – Feb 2013 · 7 mos

• Pre-Silicon Validation Process
• Simulation model for Pre Silicon Intel Processors (Haswell and Broadwell) , Where an environment is simulated for the Different modules of Intel Processors (Display, 3D, Media, Power and performance). Model is used by RTL and Architecture team to validate the Model and Functionality.
• Responsibilities Include:
• As part of Development, developed the Simulation Modules of Processor according to Processor Spec.
• Understanding the new Sub features and Programming the Model According to it
• Debugging and Fixing Issues reported by RTL and Architecture team