Rakesh Pratap Singh

Co-Founder

Bangalore Urban, Karnataka, India17 yrs 9 mos experience

Highly Stable

Key Highlights

18+ years of ASIC design and verification experience.
Expertise in system architecture to silicon delivery.
Proven track record in security module development.

Stackforce AI infers this person is a Semiconductor and Networking expert with extensive ASIC design and verification experience.

Contact

Skills

Core Skills

System ArchitectureSilicon DesignSecurity EngineeringVerification EngineeringAsic Design

Other Skills

Micro-ArchitectureRTL developmentIP-StitchingLintCDCRDCSynthesisSecure bootSecure CommunicationOTA updatesArm Corecrypto acceleratorsmemory controllersinterconnectAHB

About

Industry Veteran of 18+ years , involved in successful tapeouts/silicons of multiple asics across 180nm-16nm nodes.Started with Verification moved in Design , along the line worked closely with DFT/Physical Design teams / Software / FPGA teams. Now role spans contribution in particular domain from System Architecture to Silicon.

Experience

17 yrs 9 mos

Total Experience

5 yrs 11 mos

Average Tenure

Current Experience

Ikigge designz private limited

Strategic Advisor

Jan 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

Avyukt healthcare solutions

Strategic Advisor

Jan 2025 – Present · 1 yr 4 mos · Delhi, India · Hybrid

Qualcomm

Senior Staff Engineer

Dec 2021 – May 2025 · 3 yrs 5 mos

Nxp semiconductors

Principal Engineer

May 2017 – Nov 2021 · 4 yrs 6 mos · Noida, Uttar Pradesh, India

Work largely involves implementing common central security platform variants of which powers next generation of NXP automotive micro-controller/microprocessors.
Solution Market Name : HSE ( Hardware Security Engine ) module
Key Feature Enabled : Secure boot / Secure Communication / OTA ( over the air updates )
Product Powered : Next gen NXP Kinetis Series ( 40nm) / S32RXXX (16nm) / S32VXXX (16nm) ( S32V234 next gen )
Functional Contribution:
Coordinated with : System Architecture / Software / FPGA / Other IP's / DFT / Physical Design
inDepth involvement : Micro-Architecture / RTL development/ IP-Stitching/Lint/CDC/RDC/Synthesis (congestion/timing closure ) / works very closely with Verification teams
Key Technology/Protocol :
Arm Core ( M0+/M33/ M7 ) , crypto accelerators / memory controllers /interconnect / AHB/AXI protocols / 40nm Flash

Micro-ArchitectureRTL developmentIP-StitchingLintCDCRDC+6

Cisco

Sr. ASIC Engineer

Jul 2007 – May 2017 · 9 yrs 10 mos · Greater Bengaluru Area

worked on verification of OSI l2/l3 parser , encryption/decryption engine (AES based GCM algorithm) , Scheduler (DWRR , Absolute Priority mixed with DWRR) , High Speed Inter Asic bus SpAui (Interlaken co-developed with cortina systems) , proprietary bus talking to off chip memory , aware and briefly worked on 40/100G ethernet PCS to EDC bus.
worked on functional verification , regression management , Gate Level Simulation and formal verification for multiple modules of 35 million gate Asic .
worked on verification of SOC ( a high end feature rich multi-level Switch ) , equivalent of linecard of N7k( Cisco official name for a High End DataCenter Switch) Switch .
Currently Working as Designer for complex scheduler part of ASIC for next generation of linecards for N7k Switch family .
Specialties: Methodology :: Asic Development flow , Software Development flow , VMM ,OVM
Programming language:: c , c++ , verilog, system verilog , TCL,perl
Tools : VCS , LEC , Design Compiler , GCC ,bugzilla(bug tracker) , cvs (source version control)
Platforms:: Windows xp/7 , Linux(various distributors)