P

Pulkit Jain

CEO

San Francisco, California, United States19 yrs 1 mo experience
Highly Stable

Key Highlights

  • Over 15 years of expertise in SoC architecture.
  • Significant contributions to cache and memory innovation.
  • Proven track record in high-performance computing platforms.
Stackforce AI infers this person is a semiconductor technology expert with a focus on SoC architecture and memory design.

Contact

Skills

Core Skills

Computer ArchitectureReal-time Operating Systems (rtos)

Other Skills

Artificial Neural NetworksAXIInterconnectsHW/firmwareMemory ControllersPerformance BenchmarkingFPGAData AnalysisIntegrated Circuits (IC)Application-Specific Integrated Circuits (ASIC)Mixed SignalHardware ArchitectureVerilogLabviewPerl

About

AMD's team has benefited from over 15 years of expertise in SoC architecture and memory subsystem design. Contributions include developing hardware/firmware solutions and advancing systems with a focus on cache and memory innovation. Collaboration has driven impactful outcomes in the embedded and emergent storage domains. Previous roles at Intel involved delivering robust SoC designs and memory controller solutions, establishing a foundation of technical excellence. The aim is to enable cutting-edge advancements to empower high-performance computing platforms. Core values include precision, collaboration, and driving innovation in semiconductor technology.

Experience

19 yrs 1 mo
Total Experience
5 yrs 3 mos
Average Tenure
4 yrs 1 mo
Current Experience

Amd

Principal SoC architect - PMTS

Apr 2022Present · 4 yrs 1 mo · Santa Clara County

Computer ArchitectureReal-Time Operating Systems (RTOS)Artificial Neural NetworksAXIInterconnects

Intel corporation

SoC design/architecture engineer

Sep 2012Mar 2022 · 9 yrs 6 mos · Portland, Oregon Area

Computer ArchitectureArtificial Neural NetworksInterconnects

Globalfoundries

Research Internship

Sep 2011Jun 2012 · 9 mos · Sunnyvale, CA

Ibm

Research Internship

Jul 2009Sep 2009 · 2 mos · Yorktown heights

  • Embedded DRAM design with focus on logic compatible gain cell

University of minnesota-twin cities

PhD Research Assistant

Jan 2007Jul 2012 · 5 yrs 6 mos · Greater Minneapolis-St. Paul Area, MN

  • Embedded DRAM design

Korea university

Visiting Scholar

Jun 2006Aug 2006 · 2 mos · Gangnam-gu, Seoul, Korea

  • Oversampling based clock data recovery circuits for DRAM high speed interface

Education

Indian Institute of Technology, Kanpur

B.Tech — Electrical Engineering

Jan 2003Jan 2007

University of Minnesota

MS

Jan 2007Jan 2012

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