A

Abhinav Agarwal

Software Engineer

Seattle, Washington, United States11 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in FPGA prototyping and validation.
  • Led hardware validation for Azure Cloud Infrastructure.
  • Ph.D. in Electrical Engineering from MIT.
Stackforce AI infers this person is a Hardware Engineering expert specializing in FPGA and ASIC technologies for cloud and database solutions.

Contact

Skills

Core Skills

Fpga PrototypingEmbedded SystemsHardware ValidationFpgaFpga EmulationFpga-based Validation

Other Skills

BluespecVerilogLow Power SystemsComputer ArchitectureASICCC++MatlabProgrammingResearch

Experience

11 yrs 8 mos
Total Experience
3 yrs 10 mos
Average Tenure
4 yrs
Current Experience

Meta

Hardware Engineer

May 2022Present · 4 yrs · Redmond, WA

  • AI Silicon platforms at Meta Reality Labs
  • Pre-Silicon and Post-Silicon ML stack enablement for on-device AI
  • Full-stack HW-SW validation, AI experiences prototyping
  • Provide systems spanning multiple chip generations for ML workloads and compiler optimization
BluespecVerilogFPGA prototypingLow Power SystemsComputer ArchitectureEmbedded Systems+6

Microsoft

Senior Hardware Engineer

Oct 2017May 2022 · 4 yrs 7 mos · Greater Seattle Area

  • Hardware Validation for custom designs deployed in Azure Cloud Infrastructure
  • Validation lead for FPGA Infrastructure group supporting all FPGA deployments in Azure
  • Validation of Microsoft's Project Zipline Custom ASIC
Hardware ValidationFPGA

Oracle

2 roles

Principal Hardware Engineer

Promoted

Sep 2015Sep 2017 · 2 yrs

  • Technical lead for FPGA emulation of next-gen database accelerator, part of SPARC SoC. Completed pre-Silicon validation and enabled Software development of complete stack in parallel with RTL design. Worked with multiple teams to co-ordinate monthly FPGA image deliverables over 18-month lifecycle for product design and verification before RTL freeze. Debugged RTL and Software bugs through functional and performance validation, and enabled fast enhancement of hardware design and specification with software feedback.
FPGA emulationHardware Validation

Senior Hardware Engineer

Aug 2014Sep 2015 · 1 yr 1 mo

  • Pre-Silicon FPGA-based validation for custom database accelerator, part of the SPARC M8 SoC. Responsible for the initial FPGA-based bringup of complete Oracle Database stack on the Pre-Si design.
FPGA-based validationHardware Validation

Qualcomm

Research Intern

Jun 2009Aug 2009 · 2 mos · Greater San Diego Area

Education

Massachusetts Institute of Technology

Doctor of Philosophy (Ph.D.) — EECS

Jan 2009Jan 2014

Massachusetts Institute of Technology

Master's Degree — EECS

Jan 2006Jan 2008

Indian Institute of Technology, Kanpur

Bachelor of Technology - BTech

Jan 2002Jan 2006

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