Sushil sharma

Software Engineer

Bengaluru, Karnataka, India11 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in FPGA design and implementation.
Proficient in VHDL and Verilog for RTL design.
Hands-on experience with Xilinx tools and hardware.

Stackforce AI infers this person is a specialist in Electronics with a focus on FPGA design and implementation.

Contact

Skills

Core Skills

Fpga DesignRtl Design

Other Skills

VHDLVerilogXilinx ISEVivadoSDK developmentPCIEthernetAXI4Xilinx VivadoXilinx SDKI2CVGA ControllerMicrosoft OfficeCPowerPoint

About

1-FPGA based RTL implementation using VHDL/Verilog, functional verification, hardware board bring‐up and debugging using zynq-7020,Artix-7. 2-Hands‐on Experience in FPGA Design optimization and timing closure. 3-Communicaton protocal-: Ethernet, PCI, AXI4, I2C, SPI. 4-Professional experience in FPGA based logic implementation using industry‐standard EDA Tools,Xilinx-ISE, Vivado, Xilinx SDK.

Experience

Intel corporation

FPGA RTL Design Engineer

Jun 2022 – Present · 3 yrs 9 mos · Bengaluru, Karnataka, India · On-site

VHDLVerilogFPGA DesignXilinx ISEVivadoSDK development+1

Microchip technology inc.

Sr RTL/FPGA Design Engineer

Apr 2020 – May 2022 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Dexcel electronics designs pvt. ltd

Senior RTL/FPGA Engineer

Mar 2018 – Mar 2020 · 2 yrs · Bengaluru,Karnataka, India

Tech adityaa

FPGA Design Engineer (R&D)

Jul 2015 – Feb 2018 · 2 yrs 7 mos · India

Company Name- Tech Adityaa.
 Project 1- Design for Test (DFT) of Customize Board.
 Project description-
 Tool use- Xilinx ISE 10.1, PlanAhead 10.1, ChipScope10.1.
 Hardware use- Xilinx Spartan-3 FPGA, Xilinx Vertex-2 Pro FPGA.
 Interface use- PCI.
 Description- Writing VHDL code to test the peripheral present on the board.
 Test- Audio line test, Analog Display Interface Test, Video line test, Discrete line
Test, TTL test.
Company Name- Tech Adityaa.
 Project 2- Network Management System (NMS).
 Project description-
 Tool use- Xilinx Vivado 16.2, Xilinx SDK 16.2.
 Hardware use- Xilinx Zynq-7000 SOC ZC706 Evaluation board, AD9364 Analog Device.
 Interface use- Bare Metal Ethernet 100Mbps, AXI4, I2C.
 Memory use- DDR-3 RAM, Quad SPI Flash, Block RAM.
 Operating System- FreeRTOS.
 Description- There are two device master and slave separated with 2 Mbps wireless link.
Both device connected to local network. when master want to send data
Using wireless link then master send Hop request to slave along with
Message. When slave receive this message interrupt to processor and start
Hopping for transmission of data.
Company Name- Tech Adityaa.
 Project 3- Video Streaming using VGA Controller.
 Project description-
 Tool use- Xilinx Vivado 16.2,Xilinx SDK 16.2.
 Hardware use- Xilinx Zynq-7000 SOC Zed Evaluation board.
 Interface use- Bare Metal Ethernet 100Mbps, AXI4, VGA Controller .
 Memory use- DDR-3 RAM, FIFO.
 Description- Pixel RGB value is receives by Ethernet and store in DDR-3 RAM memory.
Then store these value in FIFO from DDR-3 RAM after that VGA controller
Read data from FIFO and display with resolution 640*480.

Xilinx ISEVivadoVHDLPCIEthernetAXI4+2

Pine training academy

FPGA Design

Aug 2014 – May 2015 · 9 mos · Govindpuram , Ghaziabad

Exposure on
1. RTL, HDL-VHDL, Synthesis , Implementation, Chipscope,FPGA Architecture - Spartan 6 and Artix 7 Family from XILINX , Coding Technique .
2. FPGA Embedded Flow using Microblaze (EDK-SDK) and Basic of C.
3. FPGA DSP Flow, using Xilinx System generator and Matlab -Simulink . Exposure FIR Filter AM ,FM, FSK Modulation.
4. FPGA development - Spartan 6 SP605 and Nexys 4.
5. FPGA Tools Expsoure - ISE and Vivado.