P

Pulkit Agrawal

Lead ML Engineer

San Francisco, California, United States10 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Machine Learning and Data Analysis.
  • Proven track record in developing deep learning models.
  • Experience in hardware design for low power systems.
Stackforce AI infers this person is a Machine Learning Engineer with expertise in hardware design and computational algorithms.

Contact

Skills

Core Skills

Machine LearningData AnalysisDeep LearningComputer VisionHardware DesignComputational Algorithms

Other Skills

OptimizationAlgorithmsData MiningLow Power SystemsNanoelectronicsPythonC++MatlabDigital Image ProcessingDigital Signal ProcessingComputer ArchitectureTeachingResearchVerilogVHDL

Experience

10 yrs 6 mos
Total Experience
3 yrs 6 mos
Average Tenure
9 yrs
Current Experience

Apple

Staff Machine Learning Engineer

Apr 2017Present · 9 yrs · Cupertino, CA · On-site

  • Foundation models training and inference optimization
Machine LearningData AnalysisOptimizationAlgorithms

Stanford university

Graduate Research Assistant

Apr 2016Dec 2016 · 8 mos · Stanford Artificial Intelligence Laboratory (SAIL)

  • I worked in Prof. Andrew Ng's Stanford ML group (https://stanfordmlgroup.github.io) on developing deep learning models for tracking and re-identifying people in retail-store videos to quantify customer engagement with products.
Deep LearningComputer VisionData Mining

Massachusetts institute of technology

Research Intern

May 2014Jul 2014 · 2 mos · Cambridge, MA

  • I worked in Prof. Anantha Chandrakasan's Energy Efficient Circuits and Systems group (https://eecsg.mit.edu) on designing a low power hardware accelerator for reconstructing light-fields from sparse samples.
Hardware DesignLow Power Systems

Indian institute of technology, bombay

Undergraduate Research Assistant

May 2012Mar 2013 · 10 mos · Mumbai Area, India

  • I worked in the Nanoelectronics Computation Lab with Prof. Swaroop Ganguly on developing computational algorithms for simulating cylindrical nanowire transistors.
Computational AlgorithmsNanoelectronics

Education

Stanford University

Master of Science (MS) — Electrical Engineering

Jan 2015Jan 2017

Indian Institute of Technology, Bombay

Bachelor of Technology (B.Tech) — Electrical Engineering (Honors) with Minor in Computer Science

Jan 2011Jan 2015

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