Sep 2021 – Present · 4 yrs 7 mos · Chandigarh, India

• Overseeing technology development at Smartbike, India's largest public bike sharing company.

Aug 2020 – Sep 2021 · 1 yr 1 mo

• Product development for online storefront for small businesses - list product catalog, online ordering and payment.

Apr 2018 – Apr 2020 · 2 yrs · Chandigarh, Chandigarh, India

• Led IoT Division with offerings in custom IoT projects, shared mobility, logistics and UAVs

Jan 2016 – Oct 2017 · 1 yr 9 mos · Cupertino, CA

• As a part of SoC Performance team, I worked on 2 architectures of memory subsystem (interconnect fabric, last level cache and memory controller) ensuring end-to-end QoS for real time agents,
• Led to a patent in interconnect design innovation involving urgency counter manipulation in arbitration algorithm.

Aug 2013 – Jan 2016 · 2 yrs 5 mos · San Diego County, California, United States

• Worked on 2 taped-out and ongoing premium tier Snapdragon projects
• Pre-silicon performance analysis of memory subsystem: performed analysis on SoC TLM platform focusing on Quality-of-Service (QoS) and bandwidth efficiency aspects of performance of memory subsystem of upcoming project; Further proposed and analyzed the impact of micro-architectural enhancements for performance bottlenecks identified
• Work with SoC architects, model developers and RTL designers on daily basis
• Responsible for releases of SystemC based model and well-versed in SoC TLM-based platform used for performance analysis
• RTL performance analysis: developed perl scripts to extract useful information from FSDB files significantly reducing the time to root cause performance issues related to QoS or efficiency
• Support for post-silicon debug issues
• Leadership: advised summer intern for automation of performance validation of model, trained new team members on architecture, analysis flows and platform updates

Jun 2009 – Jul 2011 · 2 yrs 1 mo · Greater Bengaluru Area

• Performance modeling of memory sub-system for Tegra products:
• Worked in a global team of 20 and local team of 4 to develop and triage C++ based cycle- accurate model; performed studies to test the impact of various policies on the performance,
• Adjudged as Top Contributor for the performance in first year at work
• Micro architecture, RTL Design and Verificiation for modules Image Compositor, security engine and SoC integration in upcoming Tegra projects
• Updated synthesis flow for new std cell library to be used in upcoming project