Debarun Saha — Software Engineer
Worked on one of the 7nm process node hierarchical (tile-top-level) rectilinear partitions (P&R), that includes 60730 cell count (which includes 11701 seq. cells), ports count of 28K and a dimension of 25K um by 3K um. ➢ It includes 11 sub-blocks (includes PCIE*, DDR, ARM blocks) and goes to 2 levels from top-to-down.The whole chip top consists of 84 cores and 67 sub-blocks.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and ASIC technologies.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 7 mos
Skills
- Vlsi Physical Design Flow
- Integrated Circuits (ic)
Career Highlights
- Expert in VLSI Physical Design and ASIC development.
- Experience with 7nm process node chip design.
- Strong background in Integrated Circuits and Layout Design.
Work Experience
Qualcomm
Design Engineer (2 mos)
MediaTek
VLSI DESIGN (P&R) (5 mos)
Insemi Technology Services Pvt. Ltd.
VLSI DESIGN (P&R) (1 yr 5 mos)
Alphawave Semi
VLSI DESIGN (P&R) DOMAIN. (6 mos)
MaxLinear
VLSI DESIGN (P&R) DOMAIN (10 mos)
Broadcom Inc.
VLSI (STA) Engineer (5 mos)
DIGICOMM Semiconductor Private Limited
SENIOR ENGINEER (VLSI P&R) (2 yrs 4 mos)
Frenus Tech Pvt Ltd
Intern VLSI DESIGN (P&R) (1 yr 1 mo)
Open-Silicon, Inc.
Intern in VLSI Physical Design Domain (3 mos)
RV-VLSI VLSI and Embedded Systems Design Center
Trained Full Custom Layout Circuit Designer . (7 mos)
Education
Bachelor of Technology - BTech at West Bengal University of Technology, Kolkata
ADVANCE DIPLOMA IN ASIC DESIGN. at RV-VLSI DESIGN CENTER, BANGALORE.
BTech in ECE at Calcutta Institute of Technology.(WBUT).
ADAD at RV VLSI DESIGN CENTRE.
