Ashwani Kumar

CEO

Bengaluru, Karnataka, India11 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in functional validation for Xeon servers.
  • Led post-silicon product validation from power on to volume.
  • Implemented advanced techniques like K-Mean Clustering and reinforcement learning.
Stackforce AI infers this person is a Hardware Validation Engineer with expertise in post-silicon validation and concurrency testing.

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Skills

Core Skills

Functional ValidationPost Silicon Product ValidationSystem Concurrency Traffic Generation

Other Skills

DebuggingHW/SW BIOS knobs definitionSoC feature enablementK-Mean ClusteringReinforcement learningPower ManagementPCIeCPUMemory trafficMachine LearningPython (Programming Language)Computer HardwareHardware ArchitectureWLANPerl Script

About

Functional validation (FV) of cross products for Xeon servers and concurrency for Xeon and Xeon-D servers. ● Own FV of core, cache coherency, BMC, OOBMSM, RAS, PCIE/CXL, Power Management, accelerator and side band cross products and concurrency. ● Have experience of complete post silicon product validation cycle starting from “Power On” to “Volume Validation”. ● System concurrency traffic generation for SOC including accelerator complex and cross products validation (with Power Management, PCIe, CPU, memory traffic). ● Intent verification to catch false passes and sanitize test content. ● Debug issues by localizing failure, recreating and root causing them to Silicon/RTL/firmware/tools issue using tracker logs, memory dump, performance monitoring and register reads etc. ● Define HW/SW BIOS knobs for accelerators, enable/disable in combinations and validate them on customer’s silicon configs. ● Prepare status reports, maintain progress indicators, represent the team in reviews, update meetings and collaborations. ● SoC feature enablement, testing in pre-Si using hybrid system level emulation model running on Zebu emulator. ● Implemented K-Mean Clustering for the Post-Silicon TL optimization. ● Contributed to implement the reinforcement learning for the post-Si coverage driven validation

Experience

11 yrs 9 mos
Total Experience
3 yrs 11 mos
Average Tenure
7 yrs 10 mos
Current Experience

Intel corporation

3 roles

Technical Lead

Mar 2024Present · 2 yrs 2 mos

Lead Engineer

Promoted

Jul 2020Present · 5 yrs 10 mos

Software Validation Engineer

Jul 2018Jul 2020 · 2 yrs

Functional validationPost silicon product validationSystem concurrency traffic generationDebuggingHW/SW BIOS knobs definitionSoC feature enablement+2

Mediatek

Sr Enginner

Aug 2015Jul 2018 · 2 yrs 11 mos · Noida Area, India

Qualcomm

Software Engineer

Jul 2014Jul 2015 · 1 yr · Greater Chennai Area

Education

Indian Institute of Technology Jammu

Master of Technology - MTech — Artificial Intelligence

Sep 2022Sep 2024

Gautam Buddha University

Engineer's Degree

Jan 2008Jan 2012

Greenway Public School ,Roorkee

SSC — HSC

Jan 2006Jan 2008

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