Mahesh T

Director of Engineering

Bengaluru, Karnataka, India15 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT methodologies and VLSI design.
Proven track record in SOC validation and ATPG.
Strong experience with industry-standard EDA tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT and VLSI methodologies.

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Skills

Core Skills

DftVlsi

Other Skills

VCSAutomatic Test Pattern Generation (ATPG)ATPGMBISTSOC functional validationSimulationsValidationCadence EncounterSCAN STATetramaxEDTVerdiUnixNCSimModelSim

Experience

15 yrs 10 mos

Total Experience

7 yrs 9 mos

Average Tenure

9 yrs 4 mos

Current Experience

Mediatek

Technical Manager

Jan 2017 – Present · 9 yrs 4 mos · Bengaluru, Karnataka, India · On-site

VCSAutomatic Test Pattern Generation (ATPG)DFTVLSI

Mirafra technologies

Staff Engineer

Jul 2015 – Jan 2017 · 1 yr 6 mos · Bengaluru, Karnataka, India

Cadence EncounterVCSVLSI

Wipro technologies

VLSI - DFT engineer

Jul 2010 – Feb 2023 · 12 yrs 7 mos · Bengaluru Area, India

I have worked on the following :
1)ATPG - Stuck-At, Transition Delay, and pattern simulation (timing and unit-delay)
2)MBIST: Pattern Generation and validation
3) SOC functional validation

ATPGMBISTSOC functional validationDFTVLSI