Khitish Behera

Software Engineer

Bengaluru, Karnataka, India17 yrs 6 mos experience

Key Highlights

  • Expert in Digital Design and Architecture for SoCs.
  • Proven track record in 5G and telecommunications projects.
  • Strong background in FPGA and signal processing design.
Stackforce AI infers this person is a Telecommunications and Semiconductor expert with a focus on Digital Design and Signal Processing.

Contact

LinkedIn

Skills

Core Skills

Digital Signal ProcessingFpga DesignSystem DesignModem DevelopmentSignal ProcessingSystem On Chip DesignDigital Design

Other Skills

Matlab5G signal processingSystemVerilogXilinx FPGAAXI4VerilogAlgorithm DesignArchitecture DesignSoC DesignSTAModem DesignDigital ImplementationStatic Timing AnalysisEmbedded SystemsTCL

About

- Designed IP/SoCs for new product lines across technologies - - Automotive Ethernet - Computational Storage for Data Centers - 5G Base-Station - LTE/5G Modem IPs - Computer Vision IP - Embedded Applications - Design, Architect solutions to some of fundamental problems.

Experience

17 yrs 6 mos
Total Experience
1 yr 9 mos
Average Tenure
1 yr 1 mo
Current Experience

Qualcomm

Senior Staff Engineer

Mar 2025 – Present · 1 yr 1 mo · Bengaluru, Karnataka, India · On-site

Onsemi

Member of Technical Staff

Feb 2024 – Mar 2025 · 1 yr 1 mo

Scaleflux

2 roles

Principal Engineer

Oct 2021 – Sep 2023 · 1 yr 11 mos

Principal Engineer

Oct 2021 – Sep 2023 · 1 yr 11 mos

Freelance

Design Consultant - ChipLogic. WDC, light

Dec 2020 – Mar 2021 · 3 mos

  • Studied Carrier Synchronization techniques, implemented STO and CFO algorithm (802.11n) in Matlab.
  • 5G signal processing algorithm research and implementation on Xilinx FPGA
  • AXI4 based controller design
  • Eliptic cryptography module implementation using SystemVerilog on Xiling ZynQ zcu102
  • IEEE conf paper on 5G algorithm, published on ieee : https://ieeexplore.ieee.org/document/9221397
Matlab5G signal processingSystemVerilogXilinx FPGAAXI4Digital Signal Processing+1

Sondrel ltd

Design Engineering Manager/Associate Director

May 2020 – Nov 2020 · 6 mos

  • Set up design Team for India Centre - Interviewing, Hiring RTL designers
  • Schedule Plan, Managing methodologies.. :(

Marvell semiconductor

Principal Engineer

Nov 2018 – Nov 2019 · 1 yr · Bengaluru Area, India

  • Clock and Data Recovery DSP System Design in Matlab and implemented on Verilog
  • DFE (Decision Feedback Equalizer) Design
  • DownSampler, Decimator Design
  • USXGMII module design integration
MatlabVerilogDigital Signal ProcessingSystem Design

Samsung electronics co. limited, south korea head quarters

Research And Development Engineer

Jan 2017 – Oct 2018 · 1 yr 9 mos · Suwon, Gyeonggi-do, Korea

  • Next Generation Modem Lab
  • High Throughput Channel Decoder (1. LDPC, 2. Polar Decoders) Algorithm and Architecture for 5G NR
  • MMSE, Rate Matching
  • 32Layer x 128-Antenna Matrix Inversion for MMSE, MIMO Detection
  • PUSCH,PUCCH development for NR
  • RoE-SRIO interface
Algorithm DesignArchitecture DesignModem DevelopmentSignal Processing

Mediatek

2 roles

Sr. Staff Engineer

Jan 2016 – Jan 2017 · 1 yr

  • LTE Modem Signal Processing, Research,Devlopment

Staff Engineer

Jan 2015 – Jun 2016 · 1 yr 5 mos

Texas instruments

Senior Design Engineer

Dec 2011 – Jul 2014 · 2 yrs 7 mos · Bengaluru Area, India

  • SoC Design Lead :
  • Multi-Layer AHB Interconnect Design,
  • MPUSS architecture, design/integration.
  • LMS design
  • Low-Latency Dynamically configurable Arbitration Logic
  • Full chip Synthesis, STA.
SoC DesignSTASystem on Chip DesignDigital Design

Analog devices

Member Technical Staff

Sep 2006 – Nov 2011 · 5 yrs 2 mos · Bengaluru Area, India

  • CPFSK modem receiver modelling in Matlab
  • 6th order BP-Filter Design
  • Receiver Digital Implementation
  • IP designs (LCD controller, I2C, SPI,AHB bridge)

Intel corporation

Graduate Intern

Mar 2005 – Aug 2005 · 5 mos · Bengaluru Area, India

  • L2 cache controller, Full Custom digital logic design, STA
Modem DesignDigital ImplementationModem DevelopmentDigital Design

Education

Indian Institute of Science (IISc)

MS(R) — Microelectronics and VLSI Design

Jan 2004 – Jan 2006

National Institute of Technology Rourkela

Bachelor of Engineering (BE) — Electronics and Telecommunication

Jan 1998 – Jan 2002

Senior Member, IEEE, Member Computer Society

Sep 2021 – Present

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