May 2021 – Jul 2021 · 2 mos

May 2020 – Aug 2020 · 3 mos

• Developed an algorithm to rearrange pixel data on the fly from an image sensor (CMOS) to achieve 132 FPS in 4K resolution by compressing data stream for the DDR3 AXI stream memory writers
• Optimized the image pipeline in the firmware of AXIOM Beta, an open-source camera, to maximize the FPS of the output video stream with same resource utilization
• Added support for new image sensor modes and developed a fake data generator to perform testing in the absence of the image sensor
• Implemented UNIX shell scripts which performs setup of the gateware on Zynq FPGA from the ARM cores
• Designed and validated PHY layer SerDes soft IP (Serializer-Deserializer) in VHDL that offers runtime-configurable bit-depth and word alignment using bit-slip technique for link training
• Achieved a bandwidth of 600Mbps DDR (x2) per LVDS lane in post-route timing simulation and
• automated the build system using GNU Make
• Analyzed and validated a soft IP of a UART ↔ SPI master bidirectional bridge for Lattice FPGA