Vikas Gupta — Product Engineer

I am an RTL/FPGA Design Engineer at Logic Fruit Technologies having approx 3 years of experience in RTL design and FPGA implementation. My work involves high-speed protocols including PCIe (Gen1–6) Physical Layer, Ethernet (10G/25G), AXI-4, and TCP/IP. I handle the complete FPGA implementation using Xilinx Vivado, covering RTL design, IP integration, testbench creation, I/O and timing constraints, synthesis, bitstream generation, and design porting between FPGA architectures. I am skilled in Verilog and VHDL for hardware modeling, and Python, TCL, Perl, and Shell scripting for automation. I perform linting for syntax and rule verification to ensure code quality. I have experience in validating PCIe design robustness across third-party DUTs, implementing FSMs and FIFOs, and resolving CDC, RDC, Clock Gating, and Setup/Hold violations. My debugging includes hardware analysis with ILA and VIO, simulation in QuestaSim, and network analysis via Wireshark.

Stackforce AI infers this person is a skilled RTL/FPGA Design Engineer with expertise in high-speed communication protocols.

Location: Gurugram, Haryana, India

Experience: 2 yrs 9 mos