Sirisha Reddy Satti — Software Engineer
• Total 8+ Years’ Experience as a Physical Design Engineer and Skillful in Full Chip STA • Currently Working with Qualcomm, Hyderabad as a Staff Engineer. • Hands-on experience on Block level implementations from Netlist to GDSII. • Hands-on experience in full chip STA and Block level STA for CPU blocks. • Good understanding of PGV and Context based flows. • Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/ manufacturing rules in deep-sub micron processes. • Experience with advanced technology nodes (4nm,5nm,7nm,14nm, 28nm) • Good Knowledge in physical design Flow (Floorplan, Placement, CTS and Routing) and Eco Implementations • Hands on Experience on latest tools (ICC2, ICC, Prime time, SOC Encounter, Tempus) • Strong leadership, troubleshooting skills
Stackforce AI infers this person is a Physical Design Engineer with expertise in semiconductor technology and advanced physical design methodologies.
Location: Hyderabad, Telangana, India
Experience: 11 yrs 9 mos
Career Highlights
- 8+ years as a Physical Design Engineer.
- Expert in Full Chip STA and Block level implementations.
- Hands-on experience with advanced technology nodes.
Work Experience
Qualcomm
Senior Staff Engineer (4 mos)
Staff Engineer (4 yrs 5 mos)
Senior Lead (3 yrs)
AMD
Senior Design Engineer (5 mos)
DE Level 1 (4 yrs)
Education
Master of Science (MS) at Jawaharlal Nehru Technological University
Bachelor's degree (B.E) at Sanketika Vidya Parishad Engineering College
Intermediate at Sri Chaitanya Junior College, Guntur
SSC at St.Joseph's High School, Guntur
