Sudeep Mandal

Software Engineer

Bengaluru, Karnataka, India13 yrs 6 mos experience

Highly Stable

Key Highlights

Over 10 years of experience in Physical Design.
Led multiple Full Chip SoC projects.
Filed over 20 US patents in the field.

Stackforce AI infers this person is a Physical Design Engineer with expertise in EDA and semiconductor industries.

Contact

Skills

Core Skills

Static Timing AnalysisPhysical DesignSignoff EngineeringElectronic Design AutomationDesign For Test

Other Skills

Full Chip Static Timing AnalysisConstraints DevelopmentFull Chip STAFull Chip PnRIRPV LeadMethodology DevelopmentFlow DevelopmentImplementationSignoffPnR FlowPnR Methodology DevelopmentIR drop analysis3D Integrated CircuitsPackaging

About

Currently working on Full Chip Signoff STA @google 10+ Years (Aug '12- Present) experience in Physical Design Implementation & Methodology/Flow Dev; Led Full Chip SoC PnR (Netlist to GDS) , Integration, IR, PV and Timing Closure for cutting edge designs 20+ US Patents filed Issued/pending issue , 30+ Defensive Publications Extended work includes R&D on Applied Machine learning, packaging, EDA , Modelling, 3D ICs, IoT

Experience

13 yrs 6 mos

Total Experience

2 yrs 8 mos

Average Tenure

2 yrs 8 mos

Current Experience

Google

Hardware Engineer

Sep 2023 – Present · 2 yrs 8 mos · Bengaluru, Karnataka, India · Hybrid

Full Chip Static Timing Analysis and Constraints Dev

Full Chip Static Timing AnalysisConstraints DevelopmentStatic Timing AnalysisPhysical Design

Qualcomm

Staff Engineer

Jun 2020 – Sep 2023 · 3 yrs 3 mos · Bengaluru, Karnataka, India

Full Chip STA

Full Chip STAStatic Timing Analysis

Maxlinear

2 roles

Senior Staff Engineer

Promoted

Oct 2019 – Jun 2020 · 8 mos

Full Chip PnR, IR,PV Lead
Leading Methodology , Flow Dev , Implementation & Signoff

Full Chip PnRIRPV LeadMethodology DevelopmentFlow DevelopmentImplementation+3

Staff Engineer

Apr 2017 – Oct 2019 · 2 yrs 6 mos

PnR Flow, PnR Methodology Development, IR drop analysis, Signoff Engineering

PnR FlowPnR Methodology DevelopmentIR drop analysisSignoff EngineeringPhysical Design

Globalfoundries

Member of Technical Staff (MTS)

Jul 2015 – Mar 2016 · 8 mos · Bangalore

(Global Foundries Acquired IBM Microelectronics Division with Continuation of service)
Physical Design , 3D Integrated Circuits, Packaging, Timing Analysis

Physical Design3D Integrated CircuitsPackagingTiming Analysis

Ibm

2 roles

R&D Engineer

Aug 2012 – Jul 2015 · 2 yrs 11 mos · Bangalore

Primary: Physical Design, Signal Integrity & Noise Analysis
Secondary: Statistical Timing Analysis, Electronic Design Automation, 3D Integrated Circuits, Fabrication Methods, Lithography

Physical DesignSignal IntegrityNoise AnalysisStatistical Timing AnalysisElectronic Design Automation3D Integrated Circuits+2