Satish Shet

Software Engineer

Bengaluru, Karnataka, India22 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Silicon Validation and SOC emulation.
Proven leadership in technical projects.
Extensive experience in hardware diagnostics.

Stackforce AI infers this person is a Hardware Validation Engineer with expertise in Silicon and SOC technologies.

Contact

Skills

Core Skills

Silicon ValidationTechnical LeadershipBoard Bring-up

Other Skills

SOC emulationvalidationCore switchingSOC validationPost Silicon validationMemory controller validationMemory RAS validationRAS validationPower management Block validationDesign guidelinesPlatform Design GuidelinesBoard DesignTest PlanningDebuggingPlatforms

Experience

22 yrs 3 mos

Total Experience

3 yrs 8 mos

Average Tenure

9 yrs

Current Experience

Broadcom limited

R & D Engineer - IC Design

May 2017 – Present · 8 yrs 11 mos · Bengaluru, Karnataka, India

SOC emulation and validation - Core switching group

SOC emulationvalidationCore switchingSilicon ValidationTechnical Leadership

Microchip technology

Principal Engineer

Feb 2014 – May 2017 · 3 yrs 3 mos · Bengaluru, Karnataka, India

SOC validation

SOC validationSilicon Validation

Amd

4 roles

MTS Product development Engineer

Jan 2013 – Feb 2014 · 1 yr 1 mo

Post Silicon validation
Memory controller and Memory RAS validation

Post Silicon validationMemory controller validationMemory RAS validationSilicon Validation

Senior Product Development Engineer

Aug 2011 – Dec 2012 · 1 yr 4 mos

Silicon Validation
Memory controller and RAS validation.

Silicon ValidationMemory controller validationRAS validation

Senior Product Development Engineer

Promoted

Oct 2010 – Jul 2011 · 9 mos

Silicon Validation -Electrical and functional for Power management Block, Design guidelines for AMD internal platforms

Silicon ValidationPower management Block validationDesign guidelines

Product Development Engineer- II

Dec 2008 – Oct 2010 · 1 yr 10 mos

Platform silicon team
Silicon validation, Platform Design Guidelines

Silicon validationPlatform Design GuidelinesSilicon Validation

Esqube communication solutions pvt ltd

Lead Engineer - Hardware

Dec 2005 – Dec 2008 · 3 yrs

Tata consultancy services

Engineer - Design and Development

Jan 2004 – Jan 2005 · 1 yr

Board Design, Board Bringup and validation

Board DesignBoard BringupValidationBoard Bring-up

Rit

Faculty

Jan 2004 – Jan 2004 · 0 mo

Faculty at gec

Lecturer

Jan 2003 – Jan 2004 · 1 yr

Education

Goa Engineering college, Goa, Farmagudi, Ponda

Bachelor's degree in Enggineering — Electronics and Telecommunications

Jan 2000 – Jan 2003

Government polytechnic panaji

Diploma — Electronics

Jan 1996 – Jan 1999

Sharada English High School

Jan 1989 – Jan 1994

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