Ankita Kulkarni

Software Engineer

Hyderabad, Telangana, India8 yrs experience
Highly Stable

Key Highlights

  • 8+ years in silicon validation and debugging.
  • Expertise in ARM architecture and debugging tools.
  • Proven cross-functional collaboration skills.
Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in debugging and validation processes.

Contact

Skills

Core Skills

Silicon ValidationArm ArchitectureDebuggingSystem On A Chip (soc)Programming

Other Skills

Lauterbach cmm scriptsDebug test casesPre-Silicon and Post-Silicon validationDebug InfrastructurePre-Silicon and Post-Silicon Hardware Debugging ToolsDebugging ToolsGraphics SoftwareCQtCrash reset flowScandumpDesign for Debug (DFD)Joint Test Action Group (JTAG)Post Silicon ValidationPre Silicon Validation

About

8+ years of experience in pre- and post-silicon validation, SoC debug, and DFD (Design for Debug) infrastructure. • Proficient in hardware debugging tools such as JTAG, Lauterbach (Trace32), Logic Analyzers, and system observability tools. • In-depth expertise in ARM Debug architecture with Coresight compliance. • Developed and maintained Trace32 cmm scripts for system-level validation, feature testing, and automation. • Hands-on experience in platform-level debug infrastructure setup, enabling IP-level debug and feature validation across mobile, XR, and automotive SoCs. • Specialized in crash reset flow debugging, scandump analysis, and reconstructing hang scenarios using tools like Veloce and JDR programming. • Proven skills in cross-functional collaboration with design, architecture, software, and verification teams to isolate and resolve silicon issues.

Experience

8 yrs
Total Experience
3 yrs
Average Tenure
1 yr 11 mos
Current Experience

Microsoft

Device Validation Engineer 2

Jun 2024Present · 1 yr 11 mos · Hyderabad

Qualcomm

Senior Hardware Engineer

Nov 2021Jun 2024 · 2 yrs 7 mos · Bengaluru, Karnataka, India · Hybrid

  • Working in a highly dynamic and challenging environment on Mobile, XR and Automotive SOCs in DFD (Design for Debug) team as a Qualcomm Debug Subsystem (QDSS) domain owner during Pre-Silicon and Post-Silicon phases. My role involves interaction with Design, Verification and Software teams, understand the design features, prepare the validation plan, develop Debug test cases for all the IPs and root cause the potential Silicon issues to improve the quality of SOC.
  • My areas of expertise include Lauterbach cmm scripts development for developing the test cases, system validation and debugging using ARM based debuggers, board, and SOC bringup.
  • Establishing the Debug Infrastructure for entire platform which helps individual IP owners to have Debug capabilities.
  • Job role spans End to End Feature enablement/Debugging coverage in both Pre-Silicon and Post-Silicon environment.
  • Feature undertaken by me Traces, scandump, Crash reset flow, Capture, etc.
Silicon ValidationARM ArchitectureLauterbach cmm scriptsDebug test casesPre-Silicon and Post-Silicon validation

Intel corporation

2 roles

Graphics Software Engineer

Promoted

Jul 2019Nov 2021 · 2 yrs 4 mos · Bengaluru, Karnataka, India

  • Developing debug tools for Intel Graphics which will be used by Graphics Hardware and Graphics software teams.
  • Design & Develop Pre-Silicon & Post-Silicon Hardware Debugging Tools.
  • Working on Next Generation Graphics IP Verification.
  • Software tools development those are used for microprocessor validation and debug across organization.
  • Validate and debug tool issues.
  • Support multi-user, multi-site validation tools for users which involves regular tool upgrades, supporting user requests and bug fixes.
DebuggingSystem on a Chip (SoC)Pre-Silicon and Post-Silicon Hardware Debugging Tools

Firmware Engineer

May 2018Jul 2019 · 1 yr 2 mos · Bengaluru, Karnataka, India

  • Project name: Intel Cellular Control Utility (ICCU) Tool development on M.2 7560
  • Project Description: ICCU Tool is used to start and stop RX and TX and read info back from the target, to get the real time measurement of RSSI and SNR values and to plot a graph of frequency vs Power (RSSI) based on these real time values.
  • Languages: C
  • Development Framework: Qt
  • Responsibilities:
  •  Development of new features in the Tool both frontend (GUI) and backend functionalities to enhance the usefulness of the tool.
  •  Fix bugs reported by customer by doing analysis of the logs provided.
  •  Make releases of the newly implemented change.
  •  Protex scanning of the code.
ProgrammingCQt

Intel

Graduate Technical Intern

Jul 2017Apr 2018 · 9 mos · Bengaluru, Karnataka, India · On-site

ProgrammingC

Education

Vellore Institute of Technology

Master of Technology - MTech — Embedded Systems

Jan 2016Jan 2018

GOVERNMENT COLLEGE OF ENGINEERING, JALGAON.

Bachelor of Engineering - BE — Electronics and Telecommunication

Jan 2012Jan 2016

M J College, Jalgaon

Std. 11th - Std. 12th — Science

Jan 2010Jan 2012

St. Joseph's Convent Senior Secondary School, Jalgaon (CBSE)

Std. Nursery - Std. 10th

Jan 1997Jan 2010

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