sekhar Pulipaka

Director of Engineering

Hyderabad, Telangana, India26 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Director at NVIDIA with extensive SoC expertise.
Led multiple successful chip development projects.
Trained a significant portion of ASIC development team.

Stackforce AI infers this person is a semiconductor and VLSI expert with leadership experience in ASIC development.

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Skills

Core Skills

SocStatic Timing AnalysisAsicVlsi

Other Skills

Silicon ValidationPower EstimationSynthesisTiming AnalysisChip DevelopmentDesign of I2CLow Power TechniquesSTA MethodologiesSemiconductorsEmbedded SystemsCDebuggingVerilogFunctional VerificationSystem on a Chip (SoC)

Experience

26 yrs 5 mos

Total Experience

6 yrs 7 mos

Average Tenure

15 yrs 2 mos

Current Experience

Nvidia

4 roles

Director

Promoted

Jul 2021 – Present · 4 yrs 10 mos

Sr. Manager

Promoted

Oct 2014 – Jun 2021 · 6 yrs 8 mos

Manager

Jan 2011 – Sep 2014 · 3 yrs 8 mos

Sr. Engineer

Jan 2007 – Jan 2010 · 3 yrs · Hyderabad Area, India

worked as the SOCD/Synthesis/Formal / Timing Lead for 4 SOCs.
Was involved in Silicon Validation/bringup.
Owner for Padring and PinMux functionality.
Enabled Power Estimation flow on AP designs.

Silicon ValidationPower EstimationSynthesisTiming AnalysisSoCStatic Timing Analysis

Amd

Manager

Jan 2010 – Jan 2011 · 1 yr

Portalplayer, inc.

Prinicipal Engineer

Oct 1999 – Jan 2007 · 7 yrs 3 mos

I take pride in saying that about 70% of the employees in Indian ASIC development center have been trained by me.
Leader of 4 chip development projects that were completely done from India centre, from specifications to successful Silicon validation.
Worked on Design of I2C , LCD , SPI and TWC designs
Was the Top level chip/Synthesis/DFT Lead for 6 SOCs done during my tenure @ Portalplayer
Drove Top Level TB , Synthesis and STA Methodologies for the SOC chips that went into Apple iPODs.
Worked on designing Low Power techniques for the SOCs.

Chip DevelopmentDesign of I2CLow Power TechniquesSynthesisSTA MethodologiesASIC+1