Srisidharth Kannan — Software Engineer
ASIC Design/Verification engineer . Professional experience as project engineer for 6+ years in ASIC Verification. FPGA hardware design engineer for 2 years. Experienced in Functional Verification,RTL Design,Assertions,sequences, Coverages Worked in Verilog,System Verilog languages,OVM, UVM Methodologies and Verification Environment. Experience in FPGA Altera platform for control and video transmission&reception between drone to RC Experienced in Xilinx, Cadence NC-Sim, Cadence Virtuoso, Synopsys VCS, Mentor Graphics IC-station, PDN Expert, OPNET,MATLAB Protocols learned: RAPIDIO, SRIO, PCIE, SPI
Stackforce AI infers this person is a highly skilled ASIC and FPGA design engineer with extensive verification expertise.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 11 mos
Skills
- Fpga
- Rtl Design
- Functional Verification
- Uvm
- Asic
Career Highlights
- Over 6 years of ASIC Verification experience.
- Expertise in FPGA hardware design and integration.
- Proficient in multiple verification methodologies including UVM and OVM.
Work Experience
Cadence
Principal Application Engineer (8 mos)
Qualcomm
Staff Engineer (2 yrs 1 mo)
AMD
Member Of Technical Staff (1 yr 11 mos)
Marvell Semiconductor
Senior Design Verification Engineer (1 yr 6 mos)
Wipro Technologies
Senior VLSI Engineer (1 yr 9 mos)
Yuneec USA, Inc.
FPGA Engineer (1 yr 11 mos)
Broadcom
Intern (2 mos)
Wipro Technologies
Project Engineer (2 yrs)
Education
Master's degree at San Diego State University
B.E. at Anna University Chennai
at Vidhyaa Vikas Matric
