Nidhi Chandak

Software Engineer

Bengaluru, Karnataka, India10 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL design and synthesis for high-performance GPUs.
Proficient in low power design techniques and validation.
Strong experience in cross-functional team coordination.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI technologies.

Contact

Skills

Core Skills

Rtl DesignVerilogDebuggingVhdlMicroarchitectureSynthesisProduct DevelopmentC++Cadence Tools

Other Skills

Timing FixesPost Silicon ValidationTest PlansTiming ClosureLow Power DesignOpenCVMatlabVerilog-APythonMultisimPspiceVisual C++SQLVisual StudioVisual Basic

About

Hardware Engineer with interests in the field of VLSI and Computer Architecture. Job experience in RTL Design and Synthesis using cutting edge tools.

Experience

10 yrs 9 mos

Total Experience

2 yrs 8 mos

Average Tenure

8 yrs 1 mo

Current Experience

Nvidia

Senior ASIC Design Engineer

Mar 2018 – Present · 8 yrs 1 mo · Bangalore

RTL Design for the PCIE (Gen4/Gen5/Gen6) Unit for Nvidia GPUs.
Responsible for Microarchitecture, Verilog coding and timing fixes for the Transaction Layer and Physical Layer in PCIE.
Coordination with architecture, physical design, verification and neighboring IP teams.
Post Silicon Validation and Debug for PCIE (including Gen4) unit in the chip.
Writing, scripting and executing testplans. Debugging failures and providing support for the full chip validation.
Worked on Gen4 motherboards and used Gen4 Logic Analyzer & Exerciser for the same.

RTL DesignVerilogMicroarchitectureTiming FixesPost Silicon ValidationDebugging+1

Ibm

Logic Design Engineer

Jan 2017 – Feb 2018 · 1 yr 1 mo · Bengaluru, Karnataka, India

Responsible for designing and writing VHDL code a unit in IBM Z Server chips.
Involves microarchitecture definition, design specs and timing closure with focus on low power and high frequency design techniques.
Interaction with Design Verification and Physical Design teams.

VHDLMicroarchitectureTiming ClosureLow Power Design

Apple

2 roles

Design Implementation Engineer

Jan 2016 – Dec 2016 · 11 mos · Austin, Texas Metropolitan Area

Responsible for front-end logic design with the primary focus on RTL to gate-level netlist creation (synthesis).
Learnt low power design techniques and helped reduce leakage and dynamic power of designs.

RTL DesignSynthesisLow Power Design

GPU Design Intern

May 2015 – Aug 2015 · 3 mos · Austin, Texas Metropolitan Area

Worked in the FE-Implementation team.

Sasken

Trainee

Jan 2014 – May 2014 · 4 mos · Pune/Pimpri-Chinchwad Area

PROJECT: Design and Development of Low Dropout Regulator
Market survey of available LDO designs and specifications defination.
End to end product development of 300mV dropout and 100mA, 2.5V output LDO using Cadence tools.
Scope included design, layout, GDS II file generation and developing datasheet of final product.

Robert bosch engineering and business solutions ltd.

Student Intern

Jun 2013 – Jul 2013 · 1 mo · Bangalore, India

PROJECT: Video Test solutions
Developed face and license plate detection algorithm using C++ and Open CV.
Simulated and analysed various artifacts like blur, contrast and brightness and its effects on images.
Designed testing tools: noise injector tool and video quality analysis tool.

C++OpenCV

Indian institute of technology, bombay

Junior Researcher

Jun 2012 – Jul 2012 · 1 mo · Mumbai Metropolitan Region

PROJECT: Charge Redistribution SAR ADC
System level modeling of 8 bit charge redistribution SAR ADC using Cadence tools and Matlab.
Modeled the SAR logic using Verilog-A.
Performed mismatch analysis with Monte Carlo simulations.