Daljeet Kumar

Director of Engineering

South Delhi, Delhi, India25 yrs 5 mos experience
Highly Stable

Key Highlights

  • Expert in High-Speed Serial Links design
  • Led teams for advanced Serdes projects
  • Extensive experience in CMOS technology
Stackforce AI infers this person is a Semiconductor Design Expert specializing in Analog Circuit Design and High-Speed Interfaces.

Contact

Skills

Core Skills

Analog Circuit DesignHigh Speed Link Ips

Other Skills

CMOSSerdes DesignPcie7Serdes EngineeringUSB2DIGRF4GDIGRF3GLVDSMixed-Signal IC DesignAnalog CircuitsTransmittersReceiversBandgap ReferencesIntegrated Circuit DesignIntegrated Circuits (IC)

About

- Analog Design Engineering Manager with rich experience in the design, development and management of High-Speed Serial Links (Ethernet 224Gbps/112Gbps, XSR 112Gbps, 16Gbps Serdes, USB2, USB4 40Gbps, DIGRF4G, DIGRF3G & LVDS) in multiple CMOS technologies from specification and design to test-chip silicon validation to SOC integration. - Managing and expanding Serdes design team for 112Gbps and Pcie7 in Synopsys Noida. - In Intel, along with my team, worked on High speed circuits for 224Gbps/112Gbps Ethernet PHY IP. Also lead the USB4 PAM3 40 Gbps Transmitter design. - In Synopsys, acted as analog design engineering manager for 16Gbps serdes and XSR 112Gbps RX designs. Also directly worked on TX, 5-tap DFE, Regulators and Loss of Signal (LOS) sub-blocks in serdes IP. Role involved designing sub-blocks in different technologies (TSMC 28HPCP, 28HPCP+, Auto Grade 0 eflash) and delivering IP sub-blocks meeting specifications including PCIe3, SATA, USB3, SGMII etc. Also acted as Analog domain lead and developed from scratch DP AUX PHY, the auxiliary lane of Display Port Alternate mode physical layer in different technology nodes (10FF, 16FFC, 16FFPLL, 7FF etc.). - During my long tenure at STMicroelectronics, acted as Analog Domain Lead for High speed serial Links IPs including USB2, DIGRF4G, DIGRF3G & LVDS in different technology nodes (130nm, 90nm, 65nm, 40nm, 32nm, 28nm, 28LP-FDSOI, 14LP-FDSOI, CMOS-M10, HCMOS9A). Also lead design & development of analog sub-blocks including BGR, Bias generation circuits, OTA, LDO, Serializer, de-serializer, Impedance Calibration Cells, Low-swing High speed voltage-mode & current mode drivers, Low speed high voltage tolerant High Swing Drivers, High speed receivers including CTLE, Low speed receivers, Protection block etc. Acted as USB2 design lead for almost all USB2 IPs for ST in 130nm, 90nm, 65nm, M10, 28-Bulk, 28-FDSOI technology nodes and handled design development and delivery. Handled design team of 7 designers during the development phase involving in reviews, milestone setup, detailed electrical and timing specification reviews. - In early part of my carrier, worked on Field programmable Analog Array and worked on Board level design using discrete components for Microwave Radios.

Experience

25 yrs 5 mos
Total Experience
5 yrs 10 mos
Average Tenure
2 yrs
Current Experience

Synopsys inc

Senior Manager Analog Design

Apr 2024Present · 2 yrs 1 mo · Noida, Uttar Pradesh, India · Hybrid

  • 112 Gbps MP Serdes, Pcie7 Serdes Design Manager
Analog Circuit DesignHigh speed link IPsCMOS

Intel corporation

Analog Circuit Design Engineering Manager

Feb 2021Mar 2024 · 3 yrs 1 mo · Bengaluru, Karnataka, India

Synopsys inc

Manager II

Mar 2015Jan 2021 · 5 yrs 10 mos · Noida Area, India

  • 16Gbps Serdes Engineering Manager
Analog Circuit DesignSerdes Engineering

Stmicroelectronics

Senior Staff Engineer

Dec 2003Mar 2015 · 11 yrs 3 mos

Analog Circuit DesignHigh speed link IPs

M/s himachal futuristic communications limited

Member Technical Staff

Oct 2000Dec 2003 · 3 yrs 2 mos · Gurgaon, India

Education

Delhi University

Master's degree

Jan 2000Present

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