Srinivas Manchala — Software Engineer

Having total 12+ years of experience in VLSI Physical Design. Experience in Physical Design using synopsys IC compiler2, Cadence First Encounter and Cadence Innovus. Experience in Static Timing Analysis using Synpsys PrimeTime and Tempus. Experience in LEC and Conformal Low Power. Well Known about ASIC design flow from Specifications to GDSII. Good at Floor Planning, Power Planning, Placement, CTS and Routing, finding the issues and fixing. Good knowledge on STA, DRC-LVS, Antenna fixing and IR drop analysis. Basic knowledge on coding using Verilog HDL. Exemplar in writing scripts using PERL and TCL. Expertise knowledge of Digital Design concepts. Knowledge on programming using C.

Stackforce AI infers this person is a VLSI Physical Design expert with a strong focus on ASIC design and digital systems.

Location: Hyderabad, Telangana, India

Experience: 15 yrs 3 mos