Bhargav Shukla — Product Manager
EDA test engineer to support the Palladium emulation product lines. Proficient with Agile/Scrum program management. Coding and debugging Synthesizable designs (RTL). Reviewing features specifications and creating comprehensive verification plans. Work with R&D to debug test case failures. Former FPGA Validation Engineer in Xilinx MIG Team. Involved in creating micro architecture and specifications for HW acceleration solution infrastructure. Perform subsystems and multi IP's ( DDR3, LPDDR3, DDR4, QDRII, QDRIV, RLD3) verification including lab testing. Automated and improve test suite efficiency. Holds a Master Degree (M.Tech) in VLSI Design from Vellore Institute of Technology.
Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in EDA and hardware testing.
Experience: 7 yrs
Skills
- Silicon Validation
- Data Analysis
Career Highlights
- Expert in Silicon Validation and EDA tools.
- Proficient in scripting for automation and data analysis.
- Strong background in FPGA validation and hardware troubleshooting.
Work Experience
Cadence Design Systems
Lead Product Validation Engineer (3 yrs 10 mos)
Product Validation Engineer II (1 yr 5 mos)
Western Digital
Validation Engineer (2 mos)
AMD
FPGA Validation Engineer (1 yr 9 mos)
Reliance Industries Limited
Internship (1 mo)
Education
M.tech at Vellore Institute of Technology
Bachelor of Engineering - BE at Gujarat Technological University, Ahmadabad
High School Diploma at Gujarat Technological University, Ahmadabad