Saketh Pendyala — Software Engineer

I am Masters in VLSI Design having 7 years of experience in ASIC physical design with strong background of methodology development for implementation flows. Myself looking for opportunity to work in a Organization where I can use my skills and knowledge effectively and that has vibrant atmosphere and high standards of work ethics, which will help me grow personally and professionally, thereby gaining valuable knowledge and experience in the fast growing industry Area Of Interest : Low power development and implementation. Develop physical design methodologies for full chip and block execution to improve sign-off closure. Full-Chip floor-planing , Sign-off timing (STA),

Stackforce AI infers this person is a VLSI Design expert with a focus on ASIC physical design methodologies.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 8 mos