Feb 2023 – Present · 3 yrs 3 mos · Pune, Maharashtra, India

• Led the optimization of testing frameworks for Radar, Audio, and Vision
• DSP processors, which significantly enhanced testing efficiency and reduced
• time-to-market, ensuring quicker product delivery to clients.
• Analyzed test results and isolated defects, conducting thorough root cause
• analyses and comparing code coverage with test coverage, which improved overall
• product quality and reliability, helping to minimize post-release issues.
• Developed test drivers/testbench in c/c++ for Cadence Tensilica’s Vision
• 4DR Accelerator SDK, Hardware Accelerators, and XIPC/RPC interconnect
• subsystems, streamlining testing processes and making them more effective,
• leading to faster identification of issues.
• Drove Jenkins/Python automation initiatives, which reduced manual testing
• efforts and leveraged AI to advance testing strategies, ultimately increasing
• the robustness of our testing framework and enhancing team productivity and
• confidence in product releases.
• Led validation of Xtensa Neural Network Compiler (XNNC) and NeuroWeave SDK at Cadence
• Tensilica, ensuring correctness of graph transformations, operator fusion, constant folding, and
• common subexpression elimination for Xtensa processors (HiFi, Vision, NeuroEdge).
• Directed accuracy validation for float-to-fixed quantization and low-precision (8/16-bit) arithmetic
• in AI models, using C++/Python reference models to maintain numerical stability and inference
• reliability on NeuroEdge co-processors.
• Spearheaded performance profiling and tuning of vectorized SIMD/VLIW kernels, resolving
• bottlenecks in latency, throughput, memory traffic, and DMA efficiency for optimal on-device AI
• execution.
• Managed hardware-aware testing and debugging of cache hierarchies, multi-level memory
• orchestration, and NPU-DSP interactions on Tensilica AI engines, ensuring robust low-power
• performance.