VijayGanesh SR

Director of Engineering

India12 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 10 years in silicon validation and product engineering.
Expertise in x86 and ARM based SOCs validation.
Pioneered automation in silicon validation processes.

Stackforce AI infers this person is a Semiconductor Validation Engineer with extensive experience in product development and testing.

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Skills

Core Skills

Validation EngineeringSilicon ValidationYield ImprovementTest Program DevelopmentProduct ValidationDevice CharacterizationDevice Validation

Other Skills

OptimizationDigital ElectronicsDebuggingElectronicsSemiconductorsSoCEmbedded SystemsICReliability AnalysisYield AnalysisTest Efficiency

About

Validation and Characterization Engineer with 10+ years of experience in Pre/Post Silicon validation, new product development, and product engineering. Expertise on validating x86 and ARM based SOCs. Engaged in learning about new ways to automate and simplify silicon validation. Expertise with V93K.

Experience

12 yrs 1 mo

Total Experience

4 yrs

Average Tenure

6 yrs 5 mos

Current Experience

Intel corporation

3 roles

Engineering Manager

Feb 2026 – Present · 3 mos

Technical Lead

Promoted

Feb 2022 – Present · 4 yrs 3 mos

Pre and Post Silicon Validation engineering for Digital/Analog modules.
Good experience with RTL and GLS Simulations.
Good hands on experience with ATE, Pattern generation and validation.
Accountable for 1st silicon validation (Design/Device), DOE verification, Test program review and correlation, Characterization, ATE-System correlation, Guardband definition, Reliability analysis, validation of Change Request, Failure Analysis, Customer complaints, production release, disposition, Yield and Test time/efficiency improvement and sustaining.
Collaboration with Process/Design/Simulation/Validation/Test/Failure Analysis engineering team to resolve product issues and implement solution from initial phase to sustain phase of the product life cycle.
Performed parametric, sort, final test data analysis for qualification and yield improvement.
ATE Test program review and correlation, Probe card and Load board design and qualification.
Develop test specifications by Guardbanding based on device performance at system level.
Pioneer in resolving customer issues RMA in collaboration with cross functional team.
Optimized Touchdown pattern efficiency to get best screen as a cost reduction measure.
Salvage of devices based on power/performance to meet 2nd tier customer spec.
Standardization of PTE, RMA, Yield analysis process flow with team.
Coached/ mentored new engineers.

OptimizationDigital ElectronicsDebuggingElectronicsSemiconductorsSoC+4

Product Development Engineer

Dec 2019 – Feb 2022 · 2 yrs 2 mos

Develop test program infrastructure incorporating latest Best-Known Methods.
Work with global functional teams for new product development and release to production.
Manage the flawless test and process execution by introducing new products and their ramp to
volume production in manufacturing partners.
Validate new product features, test conditions, test methodologies, and test contents during first
silicon bring-up , Multi site FTX* WSX* test bring up.
Perform test program correlation and release for high volume production.
Drive Key Performance Indicators such as test time reduction, yield debug, and quality
improvement across products.
Support qualification activities and customer return debug.

OptimizationDigital ElectronicsDebuggingElectronicsSemiconductorsSoC+4

Qualcomm

Senior Engineer

Nov 2014 – Dec 2019 · 5 yrs 1 mo

Worked as a Point of Contact for Bangalore Test team and Interact with Design Verification and DFT Engineers in on-site and off-shore to understand and resolve device characterization issues.
Developed Wafer sort (WS) and Final test (FT) programs.
Debugged Functional, Stuck-at and AT-Speed ATPG, BIST (Logic and Memory), JTAG, and IDDQ patterns.
Conversion from different test languages (VCD, EVCD, STIL ) to ATE format. Vector translation for X2, X3 and X4
Closely working with design, simulation, and DFT teams for debugging issues related to test patterns.
Participating in remote sessions with foundry for debugging test vectors and wafer sort program.
Active engagement with Foundries (TSMC, SAMSUNG and GLOBAL FOUNDRIES), Test house to resolve showstopper issues and timely resolution.
Worked on debug of compressed vectors to save tester memory. Supported DFT team in fault diagnosis and improving the fault coverage and frequency.
Developed and debugged test programs for multi-site testing for test time reduction.
Debugging RMA devices. Supported DFT/DV team in fault diagnosis and improving the fault coverage and frequency.
Responsible for WS and FT yield analysis. Validating the devices Process, Temperature and Voltage corners.
Played vital role in pre-silicon activities Simulations, Pattern generation and pattern delivery to test engineers and join them for silicon debugs for Functional Blocks from Design Verification Side.

OptimizationDigital ElectronicsDebuggingElectronicsSemiconductorsSoC+4

Tessolve services pvt. ltd.

ATE Test Engineer

Apr 2014 – Nov 2014 · 7 mos

Developed Wafer sort (WS), Final test (FT) programs.
Developed and implemented test plans on ATE from device specifications.
Debugged Functional, Stuck-at and AT-Speed ATPG patterns.
Worked with design, simulation, and DFT teams for debugging issues related to test patterns.
Worked on debug of compressed vectors to save tester memory. Supported DFT team in fault diagnosis and improving the fault coverage and frequency.
Validated the devices Process, Temperature and Voltage corners.

OptimizationDigital ElectronicsDebuggingElectronicsSemiconductorsSoC+4