Jahangir Shaikh

Software Engineer

Bengaluru, Karnataka, India25 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

24 years of experience in ASIC design and validation.
Expert in Palladium emulation and FPGA prototyping.
Led pre-silicon validation for multi-billion gate AI chips.

Stackforce AI infers this person is a Semiconductor Validation Expert with extensive experience in ASIC and SoC development.

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Skills

Core Skills

EmulationPre-silicon ValidationFpga PrototypingSystem VerificationVerification

Other Skills

AI ASICsPalladiumFPGADebuggingSimulation AccelerationPower AnalysisModel CreationRTLNetlistPXP ToolsHAPS-70/80Pre-Silicon SOC ValidationSystem Level DebuggingSystem Level VerificationValidation

About

24 years of experience in Emulation and Pre-Silicon Validation of multi-billion gate AI ASICs. Expertise in palladium emulation platform (ICE and IXCOM). Simulation acceleration at IP/Subsystem level with PCIE, AXI, APB,AHB AVIPs. FPGA prototyping knowledge (HAPS70/80). Specialties: Cadence Z1/2/3/PXP (ICE and IXCOM), SoC Verification & Validation. ARM subsystem, debugger (Lauterbach), Memory interface (HBM,LPDDR), PCIe, Verilog, SV, Perl, C,TCL, SDL Synopsys HAPS-70/80 prototyping platform.

Experience

25 yrs 5 mos

Total Experience

6 yrs 4 mos

Average Tenure

13 yrs

Current Experience

Broadcom

2 roles

Master Engineer

Nov 2022 – Present · 3 yrs 6 mos

Emulation and pre-si validation lead of Broadcom APD group's custom AI chips

EmulationPre-Silicon ValidationAI ASICs

Principal Engineer - IC design

Apr 2013 – Oct 2022 · 9 yrs 6 mos

Part of Broadcom WLAN group responsible for palladium and FPGA based emulation for wireless/combo(bt + wifi) SoCs. Single point contact for Broadcom WLAN BLR Emulation.
1. Palladium model build for various RTL and netlist releases.
2. Emulation debugs that includes pxp tools, s/w or h/w or any kind of emulation specific issues.
3. IXCOM flow bringup (pxp/Z1 with pciegen2,3,4 speedbridge), Coverage analysis with IMC.
4. Simulation acceleration with cadence PCIE AVIP.
5. FPGA Prototype build with HAPS-70/80 platform.
6. Dynamic power Analysis using Palladium.
7. CPF based model builds.
8. Various synthesizable model creation for equivalent analog component.
9. Bug fix verification and automation.
10. Enable System, ucode and s/w teams for seamless use of PXP and work with them on debug issues
11. Multisite coordination for pxp utilization and execution
12.Risk and mitigation planning and tracking
13.Contribute on improving Emulation and validation strategy
14.Interact with vendor for any PXP/Z1 specific issues.
15.SDL programming, TCL code and chip bringup.

PalladiumFPGAEmulationDebuggingSimulation AccelerationPower Analysis+2

Amd

MTS

Jul 2011 – Mar 2013 · 1 yr 8 mos · Bangalore

Pre-silicon SOC validation in emulation. Was responsible to run the latest SOC design on the emulator and test post silicon software (BIOS, Operating systems and diagnostic tests) on this emulated environment. It involves system level debugging of issues related to the design health, emulation specific and BIOS/OS, micro-code patch testing. Build emulation model on requirement basic.

Pre-Silicon SOC ValidationEmulationSystem Level DebuggingPre-Silicon Validation