Sai Chandu K

Software Engineer

Hyderabad, Telangana, India1 yr 9 mos experience

Key Highlights

  • Expert in CPU Design Verification and RISC-V architecture.
  • Strong background in teaching and mentoring engineering students.
  • Proven leadership in community development and nonprofit initiatives.
Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on CPU verification and educational mentorship.

Contact

LinkedIn

Skills

Core Skills

Cpu Design Verification

Other Skills

Load/Store unit test planAssembly-based testsRISC-VCode CoverageAMBA AXI ProtocolSystemVerilogUniversal Verification Methodology (UVM)Cache CoherencyTeam LeadershipArts & CraftsProblem SolvingUniversity TeachingMentoringSocial EntrepreneurshipNonprofit Organizations

About

Deeply fascinated by digital design and computer architecture. Eager to leverage my skills and knowledge to tackle complex challenges and exploring new avenues in the field of computer engineering and hardware design.

Experience

1 yr 9 mos
Total Experience
1 yr 9 mos
Average Tenure
1 yr 9 mos
Current Experience

Mips

4 roles

Senior Design Engineer, CPU DV Team

Aug 2025 – Present · 9 mos · Bengaluru, Karnataka, India

  • As part of the post-acquisition restructuring, my title is reclassified under the broader 'Design Engineer' family, while I continue to focus on CPU Design Verification.
CPU Design Verification

Engineer, CPU Design Verification

Promoted

May 2025 – Aug 2025 · 3 mos · Bengaluru, Karnataka, India

CPU Design Verification

Associate Engineer, CPU Design Verification

Jul 2024 – Apr 2025 · 9 mos · Bengaluru, Karnataka, India

  • 1. Understanding the core design implementation based on the ISA - MAS Review
  • 2. Developing Load/Store unit test plan and writing assembly-based tests to validate architectural and microarchitecture features
  • 3. Track bugs with detailed triaging, root-cause analysis
CPU Design Verification

Intern, CPU Design Verification

Jan 2024 – Jun 2024 · 5 mos · Bengaluru, Karnataka, India

RISC-VCode CoverageAMBA AXI ProtocolCPU Design Verification

Nvidia

Intern, CPU Design Verification Team

Jul 2023 – Dec 2023 · 5 mos · Bengaluru, Karnataka, India · On-site

SystemVerilogUniversal Verification Methodology (UVM)Cache CoherencyCPU Design Verification

Birla institute of technology and science, pilani

Teaching Assistant

Sep 2022 – Dec 2022 · 3 mos · Hyderabad, Telangana, India

  • Teaching Assistant for the Electromagnetic Theory course for junior year students.
Problem SolvingUniversity TeachingMentoring

Arts & deco

CoStAAn

Jul 2022 – May 2023 · 10 mos

  • Council of Student Technical Activities Nominee
Team LeadershipArts & Crafts

Nirmaan organization

Participative Community Development Lead

Jul 2021 – Oct 2022 · 1 yr 3 mos

Social EntrepreneurshipNonprofit Organizations

Army base workshop

Summer Intern

May 2021 – Jul 2021 · 2 mos · Pithoragarh, Uttarakhand, India

Education

Birla Institute of Technology and Science, Pilani

M.Sc. with B.E (Dual Degree) — Physics and Electronics Communications

Jan 2019 – Jan 2024

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