May 2023 – Jul 2023 · 2 mos · Bengaluru, Karnataka, India · On-site

• Enhanced and optimized checkers, made them more generic and scalable for future SOC requirements.
• Added new checks to identify DCT(Direct Cache Transfers) and assess the idleness of different cores.
• Added occupancy checks for stress detection and Fixed multiple testbench bugs in production.

Nov 2022 – Apr 2023 · 5 mos · Varanasi, Uttar Pradesh, India

• Organized I-Chip, a Verilog-HDL based event under Udyam'23.
• Conducted multiple workshops and designed problem statement for the event.