Surendra Mahala — CTO
19 Years of Experience in SystemC/TLM2.0 based Virtual Prototype Model Development/Verification and RTL IP/SOC Verification. Skill Set: - People Management - Technical Project Leading - System level debugging - C, C++, System C and TLM2.0 Model Development and Verification - UVM-SystemC Cosimulation - RTL IP Verification using System C - RTL SOC Verification - VHDL and Verilog - Perl and Shell Scripting
Stackforce AI infers this person is a seasoned leader in semiconductor and ASIC development.
Location: Bengaluru, Karnataka, India
Experience: 21 yrs 5 mos
Skills
- Technical Project Leading
- People Management
Career Highlights
- 19 years of experience in verification and model development.
- Expert in SystemC/TLM2.0 and RTL IP/SOC verification.
- Proven leadership in technical project management.
Work Experience
Microsoft
Principal Software Engg Mgr (2 yrs 8 mos)
Synopsys Inc
Sr. Manager, R&D (1 yr 3 mos)
Western Digital
Senior Manager, ASIC Dev Engineering (3 yrs 9 mos)
SanDisk®
Manager, ASIC Dev Engineering (1 yr 7 mos)
Staff Engineer (2 yrs 7 mos)
Intel Corporation
Technical Lead (3 yrs 6 mos)
STMicroelectronics
Sr. Design Engineer (4 yrs 8 mos)
DRDO, Bangalore
Scientist-B (1 yr 5 mos)
Education
Bachelor of Technology (B.Tech.) at Malaviya National Institute of Technology Jaipur
