May 2017 – Apr 2019 · 1 yr 11 mos · Bengaluru Area, India

• Working as Physical Design Engineer in VPG Team as part of Graphics design for Intel's next generation processors. Worked as Partition Execution Owner(PEO), responsible for converging blocks in terms of timing and routing. Hands on experience from Register Level Synthesis (RLS) to GDSII convergence. Performed synthesis, place and route, static timing analysis, CTS, ECO, timing closure and design rule checks. Worked close to floorplan team for bus planning, port placement, macro placement, resizing, reshaping and utilization issues. Have good knowledge of Floorplan. Analyzed timing at different corners and have given manual ECO receipes to fix timing, caliber(DRC), signal integrity (crosstalk, EM and IR) violations. Experience to converge critical blocks. Worked on 22nm, 14nm and 10nm technology nodes.
• Have received recognition for solving complex inter partition caliber(DRC) violations and routing issues. Also received certificate for result orientation work.

Nov 2016 – May 2017 · 6 mos · Hyderabad Area, India

• Have done research work for design of ”IndianMicroprocessor” (projected to be India’s first Indigenously developed Microprocessor for defence). Worked on Defence Research and Development Organization (DRDO) for a project in collaboration with CDAC

Jul 2014 – May 2016 · 1 yr 10 mos

• Responsible for conducting labs and tutorials, Assisting in design of course materials, Evaluating students.